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Soc Encounter Timing Analysis

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Newbie level 5
Dec 2, 2010
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Hi all,
I am using the encounter for the first time. I have loaded the design, done the routing also the clock tree. Can view the timing analysis. But how do i make changes to timings like reduce slew rate , delay etc? Is there any graphical option where i can do something like simulation or do i need to make changes to sdc and lib file everytime re-load n check the timing report? This question may sound sillyand basic, but I would really appreciate if someone could help me out.

Also in my design, I cannot display the clock tree. I can view the FF's in the analyse clock-tree window though the Min/Max path is unavailable to me. How do I analysize it?

Hi ,

There will be lot of analysis to reduce delay and timing violations .
I hope you have gone thru the flow like placement, CTS and then routing.
U need to analyze the path which cell is causing more delay and is it due to heavy load its driving or due to worst slew it is getting.
I think you r new to Physical design,correct if i am wrong. You cannot make changes to SDC or Libraries. What STA does is it will calculate delays of cells in the constrained paths by using Input slew and output load of tat cell. The delay is taken by two dimensional delay table in the library.

Once you have built CTS there will be a Clock Report file is generated. You can check in tat. If you have built clock tree correctly then the clock will be displayed properly.

I think you r analyzing timing aft route using timeDesign -postRoute rt??
Pls let me know any information you want.
Yes..u are right. I am new to Physical Design but regarding the timing analysis i m doing the preCTS one. I have got reports (preCTS) and they display values.
The clock tree analysis doesn give me an option to find min/max path. CAn u suggest what changes/corrections I should make for the display? If the clock tree isnt working how will I get the values with zero violation paths? Is there any book, manual or papers U would suggest me to read to get more details about the timing values and efficiency?

---------- Post added at 00:28 ---------- Previous post was at 00:27 ----------

Thanks a lot for ur help

You are doing preCTS analysis and Clock tree synthesis, rt?? Clock tree analysis the min/max path where you r seeing?? As far i know it reports in Clock report nd log also for each clock in your design. The min/max path for the CTS is the min/max path clock is reaching to register. ie the shortest and longest path of the clock . For building clock tree you can refer Encounter User Guide and for commands encounter text command reference. For concepts on STA , go for "STA a practical approach" by J. Bhaskar and Rakesh Chada. You can download from net. Its a must read book for all STA guys.

"If the clock tree isnt working how will I get the values with zero violation paths? "
Am not able to understand what you are stating here. Once Clock tree is built clock network delays comes in to picture. After CTS you need to propogate your clocks and then report timing. There you will see "Clock delay (prop)" if this delay is zero then clocks are not propagated ie they r ideal.
yes, I am doing preCTS clock tree analysis. There is an option in the analysis window find -> min/max path, but I cannot access that( its disabled). Yep , I do find clock reports for fanout, cap etc.
By that sentence, I meant I get the report for timing giving values with no violation paths.In that case I think my clock tree does work. Correct me if its wrong.

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