What do you mean by "in Cadence" ?But, doing the transistor level simulation in Cadence
I think your situation is noise floor up over broadband.I am showing higher noise floor than what is supposed to be, so SNR is 63dB.
Using the same OTA and comparator,
I have designed 2nd order CIFB sigma delta with 82dB SNR,
but my problem is with CIFF sigma delta.
What do you mean by "in Cadence" ?
Do you think the simulation in MathWorks makes sense ?
I think your situation is noise floor up over broadband.
Right ?
Causes of noise floor up over broadband are
(1) Dirty waveform of Feedback Current DAC, e.g. Glitch Noises
(2) Less accurate of feedforward summation
(3) Feedback Current DAC Timing
About (1), you use NRZ DAC, so interference between symbol can occur.
interference between symbol causes noise floor.
However you say there is no problem in CIFB.
So (1) is not your primary cause.
About (3), your sampling frequency=1MHz is relative slow.
However feedback timing is severe in CIFF than CIFB.
I think (3) is your primary cause.
No, it does not make sense at all.The simulation in Mathworks makes sense
No, if you mean ADE(Analog Design Environment), it does make sense.but the simulation in Analog Environment in Cadence does not.
Show me Spectrum of Simulink result.I attached the spectrum of the ADC output.
No.By feedback current DAC timing, do you mean jitter?
You must not insert delay between Quantizer and DAC.I am trying placing a delay block before applying the comparator output to DAC to see if that is the case.
Did you do all Verilog-A models simulation ?Could you please take a look at the spectrum?
I would appreciate if you could provide me with your comments.
You use active summation for feedforward path.I have also tried ideal opamp for doing summation, it did not work either.
Here you have to show us simulator name and its version you use, since we can launch various simulators from Cadence ADE.
Actually, I have no idea. I just set the simulation stop time based on input frequency.BTW, what solver do you use in Simulink, fixed time step or adaptive time step ?
No, I did the system level simulation in Simulink and then moved to schematic and transistor level simulation in Virtuso.Did you do all Verilog-A models simulation ?
Here, they are ideal-OTA, ideal-OPAmp, ideal-quantizer, ideal-Current-DAC.
I checked the link, it was helpful in defining the resistor values for passive summation. Using this link, I could calculate resistor values corresponding to K4 and K5. In attached Simulink file, I assume that capacitors C1 and C2 are the exact values as c1 and c2 in the first and second integrator, and corresponding resistor of K3 would be R=1/K3. Is that right?You use active summation for feedforward path.
However you use 1bit-quantizer, so gain is not required for active summation.
https://www.designers-guide.org/Forum/YaBB.pl?num=1494005387
Show us over plot Spectre Result and Simulink Result.I attached spectrum of Simulink result.
System level simulation for CT-DSM-ADC is very easy by using Verilog-A in Cadence Spectre.No, I did the system level simulation in Simulink
and then moved to schematic and transistor level simulation in Virtuso.
No.By changing the timing of quantizer,
do you mean changing the duty cycle of the clock?
Yes.Or changing the comparator's decision edge?
Wrong.There is only one feedback in all of them.
Completely wrong.I used two DACs in schematic Spectre in order to relax the OTA output current.
Both of those DACs are synchronous (both of them are ON or OFF at the same time,
since the switches for upper DAC are pmos and the switches for the lower DAC are nmos.).
Which means both of those should be considered as one DAC.
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