SNR issue with continuous time 2nd order feedforward sigma delta

[FAMA89]

Hi,

I am designing a 2nd order continuous time feedforward sigma delta where the input is current. the design parameters are: OSR=128, sampling frequency=1MHz, OTA gain=70dB, OTA UGBW=2.5MHz, NRZ DAC current=12uA. I have done the simulatin in Simulink/MATLAB achieving 87dB SNR. But, doing the transistor level simulation in Cadence, I am showing higher noise floor than what is supposed to be, so SNR is 63dB. The output voltages of the opamps are in the swing range, so the opamp saturation wouldn't be an issue. I have attached the sircuit schematic. I would appreciate if anyone could help me with that.

Using the same OTA and comparator, I have designed 2nd order CIFB sigma delta with 82dB SNR, but my problem is with CIFF sigma delta.

Thank you.

 

[pancho_hideboo]

But, doing the transistor level simulation in Cadence

What do you mean by "in Cadence" ?

Do you think the simulation in MathWorks makes sense ?

I am showing higher noise floor than what is supposed to be, so SNR is 63dB.

I think your situation is noise floor up over broadband.
Right ?

Using the same OTA and comparator,
I have designed 2nd order CIFB sigma delta with 82dB SNR,
but my problem is with CIFF sigma delta.

Causes of noise floor up over broadband are
(1) Dirty waveform of Feedback Current DAC, e.g. Glitch Noises
(2) Less accurate of feedforward summation
(3) Feedback Current DAC Timing


About (1), you use NRZ DAC, so interference between symbol can occur.
interference between symbol causes noise floor.
However you say there is no problem in CIFB.
So (1) is not your primary cause.

About (3), your sampling frequency=1MHz is relative slow.
However feedback timing is severe in CIFF than CIFB.
I think (3) is your primary cause.

 

[FAMA89]

Thank you, pancho_hideboo, for your reply.

What do you mean by "in Cadence" ?

Do you think the simulation in MathWorks makes sense ?

The simulation in Mathworks makes sense, but the simulation in Analog Environment in Cadence does not.

I think your situation is noise floor up over broadband.
Right ?

Yes, exactly. the noise floor over broadband is high. I attached the spectrum of the ADC output.

Causes of noise floor up over broadband are
(1) Dirty waveform of Feedback Current DAC, e.g. Glitch Noises
(2) Less accurate of feedforward summation
(3) Feedback Current DAC Timing


About (1), you use NRZ DAC, so interference between symbol can occur.
interference between symbol causes noise floor.
However you say there is no problem in CIFB.
So (1) is not your primary cause.

About (3), your sampling frequency=1MHz is relative slow.
However feedback timing is severe in CIFF than CIFB.
I think (3) is your primary cause.

I have tried ideal current DAC (a current source) previously and couldn't get higher SNR than 63dB. So dirty waveform of feedback DAC would not be the case.
I have also tried ideal opamp for doing summation, it did not work either.
By feedback current DAC timing, do you mean jitter? I am trying placing a delay block before applying the comparator output to DAC to see if that is the case.

Could you please take a look at the spectrum? I would appreciate if you could provide me with your comments.
Thank you.

 

[pancho_hideboo]

The simulation in Mathworks makes sense

No, it does not make sense at all.

but the simulation in Analog Environment in Cadence does not.

No, if you mean ADE(Analog Design Environment), it does make sense.
Use correct terminologies.
See https://www.edaboard.com/showthread.php?354854#10

Here you have to show us simulator name and its version you use, since we can launch various simulators from Cadence ADE.

However your problems are not simulator's issues.

I attached the spectrum of the ADC output.

Show me Spectrum of Simulink result.

BTW, what solver do you use in Simulink, fixed time step or adaptive time step ?

By feedback current DAC timing, do you mean jitter?

No.
Try to change DAC timing, e.g. rising-edge to falling-edge.

I am trying placing a delay block before applying the comparator output to DAC to see if that is the case.

You must not insert delay between Quantizer and DAC.

Could you please take a look at the spectrum?
I would appreciate if you could provide me with your comments.

Did you do all Verilog-A models simulation ?
Here, they are ideal-OTA, ideal-OPAmp, ideal-quantizer, ideal-Current-DAC.

If your mapping to R and C from coefficents and sampling frequency is correct, it is easy to get almost same Spectrum as Simulink.

I have also tried ideal opamp for doing summation, it did not work either.

You use active summation for feedforward path.
However you use 1bit-quantizer, so gain is not required for active summation.

https://www.designers-guide.org/Forum/YaBB.pl?num=1494005387

Confirm values of R and C and timing of DAC.

 

[FAMA89]

Here you have to show us simulator name and its version you use, since we can launch various simulators from Cadence ADE.

I am using Cadence Virtuso and Cadence Spectre as simulator.
I don't think my problem is simulator's issue.
I attached spectrum of Simulink result.

BTW, what solver do you use in Simulink, fixed time step or adaptive time step ?

Actually, I have no idea. I just set the simulation stop time based on input frequency.

Did you do all Verilog-A models simulation ?
Here, they are ideal-OTA, ideal-OPAmp, ideal-quantizer, ideal-Current-DAC.

No, I did the system level simulation in Simulink and then moved to schematic and transistor level simulation in Virtuso.
Since my design is continuous time with current as its input, I could not find useful materials in order to learn how to design the system level parameters for CIFF, so I designed it based on try and error in Simulink. If you know any material that could help me, I would appreciate if you share the name of those with me.

You use active summation for feedforward path.
However you use 1bit-quantizer, so gain is not required for active summation.

https://www.designers-guide.org/Forum/YaBB.pl?num=1494005387

I checked the link, it was helpful in defining the resistor values for passive summation. Using this link, I could calculate resistor values corresponding to K4 and K5. In attached Simulink file, I assume that capacitors C1 and C2 are the exact values as c1 and c2 in the first and second integrator, and corresponding resistor of K3 would be R=1/K3. Is that right?

 

[pancho_hideboo]

I attached spectrum of Simulink result.

Show us over plot Spectre Result and Simulink Result.

No, I did the system level simulation in Simulink
and then moved to schematic and transistor level simulation in Virtuso.

System level simulation for CT-DSM-ADC is very easy by using Verilog-A in Cadence Spectre.
See https://www.edaboard.com/showthread.php?293780

At least, I think you use behavioral model DAC.

Show me followings,

Relation between {R, C, DAC's Amplitude} and {c1, c2, k1, k3, k4, k5}.
Here these mappings are dependent on sampling frequency.

Full Scale of Input Current.

I think your mappings are wrong.

BTW, did you try to change timing of quantizer.
For example, rising-edge to falling-edge.

See
https://www.amazon.com/Understandin...onic-Systems/dp/1119258278/ref=dp_ob_image_bk

https://www.wiley.com/en-us/Understanding+Delta+Sigma+Data+Converters,+2nd+Edition-p-9781119258278

 

[FAMA89]

I attached the over plot results and also attached the schematic in Spectre.

I am trying to learn how to do the simulation in Velirog-A and do the system level simulation.

Here are the parameters:
Simulink:
c1=150e-12
c2=20e-12
K1=12.4 e-6
K3= 5e-6
K4=0.32
K5=0.42

Spectre:
C1=150pF
C2=20pF
K1=12.4uA (DAC's Amplitude)
R3=200kOhm (1/K3)
R4=1.325kOhm
R5=1kOhm

Full scale of input current is the same as DAC K1 (12.4uA). The amplitude of the input current that I am testing the circuit with that, is 80% of the DAC current.
sampling frequency=1MHz

Could please explain how I should do the mapping? I would appreciate that.

By changing the timing of quantizer, do you mean changing the duty cycle of the clock? Or changing the comparator's decision edge? I have done both and didn't see any difference in result.

Thank you.

 

[pancho_hideboo]

https://www.edaboard.com/attachment.php?attachmentid=148987&d=1536721807

https://www.edaboard.com/attachment.php?attachmentid=149039&d=1536948096

These are completely different.

At least, first one is consistent with https://www.edaboard.com/attachment.php?attachmentid=149023&d=1536854940

Two feedbacks and passive summation in last one.

https://www.edaboard.com/attachment.php?attachmentid=149003&d=1536771252

https://www.edaboard.com/attachment.php?attachmentid=149038&d=1536948085

These are also different.
There is no DC-component in first one.

DC-component is reasonable, since your structure is single-ended.

Show us truth.
Keep consistency through thread.

 

[FAMA89]

There is only one feedback in all of them. I used two DACs in schematic Spectre in order to relax the OTA output current. Both of those DACs are synchronous (both of them are ON or OFF at the same time, since the switches for upper DAC are pmos and the switches for the lower DAC are nmos.). Which means both of those should be considered as one DAC.

I used active summation at first, but after you send me a post regarding passive summation I changed it to passive summation and updated the resistors' values and simulated the circuit again.
So, the spectrum result that is shown in my previous post, is based on passive summation and exact schematic that I attached with that.

There is DC component for sure. In the first spectrum in my first post, I removed the DC in MATLAB while I was plotting the figure (by mapping the quantizer output to -1 and 1). Because I am using single-ended structure, there exists the DC component for sure. In order to prevent any misunderstanding, please ignore the first spectrum.

Sorry if I mislead you.
Thank you.

 

[pancho_hideboo]

By changing the timing of quantizer,
do you mean changing the duty cycle of the clock?

No.

Or changing the comparator's decision edge?

Yes.

There is only one feedback in all of them.

Wrong.

I used two DACs in schematic Spectre in order to relax the OTA output current.
Both of those DACs are synchronous (both of them are ON or OFF at the same time,
since the switches for upper DAC are pmos and the switches for the lower DAC are nmos.).
Which means both of those should be considered as one DAC.

Completely wrong.

Surely see https://www.edaboard.com/attachment.php?attachmentid=149038&d=1536948085

Your situation is not noise floor up over broadband.

Obviously, Spectre's NTF is different from Simulink’s one.
Order of NTF is reduced.

If you would like to keep Spectre's structure, you have to add feedback also in Simulink.