Hi,
Schematic:
* There are still all recommended capacitors missig at the FTDI chip. PLEASE read the datasheet and follow the ruels. You really risk that your circuit fails.
I will ignore them in future.
Board:
It looks more tidy now. And the bottom GND plane is very solid.
I ignore now the DRC violations regarding outline/dimension. I assume you know what you do.
I ignore now the mistakes made in the libraries.
Copper pour on TOP side.
You ask.. therefore I try to explain again:
* It is not connected to a signal. It is not "GND" it is not "COM" it is just floating.
* floating copper pour is definitely worse than no copper pour.
* especially bad regarding EMI/EMC are the nasty orphans.
If you ask me: I´d delete the complete TOP copper pour.
May I ask, why you insist on the copper pour?
There is a via next to the ICSP connector. It is useless. You see it is not connected to the TOp copper nor it is connected to BOTTOM copper. It´s just a plated hole, isolated to anything.
Now you have 6 wires in the dimension layer. Temporarily move the right bottom corner to see the hidden two. Remove them to avoid problems at PCB production.
Not wrong, but not nice, too. The 3V3 connection to the ESP. I talk about the horizontal trace, unnecessarily fed to the bottom, then after some mm it is fed to the top again. A single via will do.
(If you rotate T2 90° CW then you can do without via)
Btw: T2 is THM. Why not SMD. BC847.
Klaus