Hi vlsi_eda_guy,
Thanks a lot for the clear explation on SDD. But I have one more doubt.
"Now the current ATPG tools in transition tries to detect the fault on the shortest path that is with maximum slack , but if we some how target the same fault on the longest path i.e with least slack then the chances that even the small fault will get detected when on ATE. "
The "longest path" that you have talked about, does it need to be a critical path ? Or does it mean the longest path having the target faut in it and this longest path may not necessarily be a critical path of the design??
Thanks
Anjana