1. when slew is slow as u said there would a high current flowing from VDD to VSS for a long time causing an increase in power as well as it would slow down you cell and increase the delay of your cell as delay is a function of both input slew and output load
2. if the slew is very high there a sudden change in current this would make inductance effect dominant as e = -L di/dt and causing supply bounces.
i understand when slew is high meaning,
o->1 or 1->0 takes long time,
by which more current is passing thru inverter(lets say)
by opening the PMOS and NMOS longtime.
I had a question whey they open up,
even after describing the above fact, they are not satisfied.