slack optimization in RTL compiler

[kannanunni]

how to optimize slacks which is negative in cadence RTL compiler to an optimum value manually(other than tool optimization)..
what are the methods used to?

other than transistor sizing and buffer insertion..??

please do reply in detail..
i'm new in this area..

 

[sharath666]

You can pipeline long combinational paths i.e. add registers at suitable points to reduce the combinational delay. This will improve your slack results...

 

[layowblue]

Assuming you do not intend to change RTL logic, hvt/svt/lvt selection might be an option, which is sort of transistor sizing.
Current RC tools are smart enough to handle all possible circuit optimization well enough. If you still get timing violations, you'll have to either allow transistor resizing(at expense of more power for speed), or re-code your RTL.

 

[kannanunni]

Assuming you do not intend to change RTL logic, hvt/svt/lvt selection might be an option, which is sort of transistor sizing.
Current RC tools are smart enough to handle all possible circuit optimization well enough. If you still get timing violations, you'll have to either allow transistor resizing(at expense of more power for speed), or re-code your RTL.

hvt/svt/lvt selection means?
swapping HVT and LVT cells??

 

[sharath666]

hvt/svt/lvt selection means?
swapping HVT and LVT cells??

LVT cells give a better timing performance. So replace cells in worst paths with LVT cells so that slacks can be reduced.

 

[kannanunni]

LVT cells give a better timing performance. So replace cells in worst paths with LVT cells so that slacks can be reduced.

But it might affect the power dissipation right?

 

[sharath666]

But it might affect the power dissipation right?

That is true. So that is finally upto your design. Whether power or timing is important.

 

[kannanunni]

That is true. So that is finally upto your design. Whether power or timing is important.

In which situations resizing is effective?
other than this HVT,LVT swap..?

 

[layowblue]

depending on technology(40n, 28n), you can check lib doc to figure out how much timing margin you can gain by switching a standard HVT NAND cell to SVT/LVT ones.
Also, you can set RC tool to use SVT/LVT for critical timing path, and RC will give you a report regarding how many SVT/LVT cells are used.