Skew in prects stage is modeled as 0ps

[jsathish.challenge]

Hi to all,
In my design the skew is set as 0ps for pre CTS constraints.Why they always set the skew =0ps .

 

[itsmeteja]

When there is no clock tree present in the design, ideally clock will be assumed to reach all the registers at the same time. But post clock tree is built due to many effects (loading,parasitic,CTS algo) there might be slight differences in the arrival time to the registers.