library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity test is
port
(
IN_SOME_DATA : in std_logic_vector ( 15 downto 0 ) ;
IN_SOME_COEFFICIENT : in std_logic_vector ( 11 downto 0 ) ;
OUT_RESULT : out std_logic
) ;
end entity test ;
architecture rtl_test of test is
component multiplier is
port
(
dataa : in std_logic_vector ( 11 downto 0 ) ;
datab : in std_logic_vector ( 15 downto 0 ) ;
result : out std_logic_vector ( 27 downto 0 )
) ;
end component multiplier ;
type result_array is array ( 0 to 199 ) of std_logic_vector ( 27 downto 0 ) ;
signal result : result_array ;
signal prevent_optimization : std_logic_vector ( 0 to 199 ) ;
begin
OUT_RESULT <= '1' when prevent_optimization = ( prevent_optimization ' range => '1' ) else '0' ;
generate_multipliers : for index in 0 to 199
generate
multiplier_instantiation : multiplier
port map
(
dataa => IN_SOME_COEFFICIENT ,
datab => IN_SOME_DATA ,
result => result ( index )
) ;
prevent_optimization ( index ) <= result ( index ) ( 27 ) ;
end generate ;
end architecture rtl_test ;