single cycle processor mips 32 bit (data memory)verilog

[funjoke]

i already edited my code for the data memory ,now i facing error with this line


assign address_select = (address[31:7] == BASE_ADDRESS);


code:
module mem32(clk, mem_read, mem_write, address, data_in, data_out);
input clk, mem_write;
input [31:0] address, data_in;
output [31:0] data_out;
reg [31:0] data_out;

parameter BASE_ADDRESS = 25'd0;

reg [31:0] mem_array [0:31];
wire [4:0] mem_offset;
wire address_select;

assign mem_offset = address[6:2]

assign address_select = (address[31:7] == BASE_ADDRESS); // address decoding


always
begin

if (address_select == 1'b1)
begin

data_out = mem_array[mem_offset];

end
else data_out = 32'hxxxxxxxx;
end

// for WRITE operations
always @(posedge clk)
begin
if (mem_write == 1'b1 && address_select == 1'b1)
begin

mem_array[mem_offset] <= data_in;
end
end
end module




CAN ANYBODY know what the problem ?

 

[dilinx]

i already edited my code for the data memory ,now i facing error with this line


assign address_select = (address[31:7] == BASE_ADDRESS);

one thing i can make out is, u missed semicolon for previous statement
i.e.

assign mem_offset = address[6:2]

 

[funjoke]

can anybody explain on how this data memory code work on in this single cycle mips ?

 

[funjoke]

shall anyone help on test bench of data memory?