single cycle processor mips 32 bit (data memory)verilog

[funjoke]

my code i have written is non-syntesizable .is there any wrong of it ?


module mem32(clk, mem_read, mem_write, address, data_in, data_out);
input clk, mem_read, mem_write;
input [31:0] address, data_in;
output [31:0] data_out;
reg [31:0] data_out;

parameter BASE_ADDRESS = 25'd0;

reg [31:0] mem_array [0:31];
wire [4:0] mem_offset;
wire address_select;

assign mem_offset = address[6:2]

assign address_select = (address[31:7] == BASE_ADDRESS); // address decoding


always @(mem_read or address_select or mem_offset or mem_array[mem_offset])
begin

if (mem_read == 1'b1 && address_select == 1'b1)
begin
if ((address % 4) != 0)
$display($time, " rom32 error: unaligned address %d", address);
data_out = mem_array[mem_offset];
$display($time, " reading data: Mem[%h] => %h", address, data_out);
end
else data_out = 32'hxxxxxxxx;
end

// for WRITE operations
always @(posedge clk)
begin
if (mem_write == 1'b1 && address_select == 1'b1)
begin
$display($time, " writing data: Mem[%h] <= %h", address,data_in);
mem_array[mem_offset] <= data_in;
end
end

// initialize with some arbitrary values

integer i;
initial begin
for (i=0; i<7; i=i+1) mem_array = i;
end
endmodule

 

[user_asic]

Initial-begin is not syntesizable. Incorporate an always block which assigns arbitrary values on reset. Additionally some synthesis tools, such as Xilinx XST, allow one to initialize variable, but it will only do it once on power on of the device. Therefore, its best practice to to use an always block with reset to restore variables to arbitrary values.

 

[funjoke]

What do you mean by this ?i not understand ,can you show me in my code on how to solve this problem

 

[user_asic]

The initial construct is NOT synthesiable. Do something like this:

// initialize with some arbitrary values
//make i a reg

always @(posedge reset)
begin
if(reset) begin
for (i=0; i<7; i=i+1)
mem_array = i;
end
end

You can also use a counter to avoid the for() loop.

 

[funjoke]

always @(posedge reset)
begin
if(reset) begin
for (i=0; i<7; i=i+1)
mem_array = i;
end
end


ADD THIS CODE AT WHERE ?at the beginning or ?still got any wan to change ?

 

[user_asic]

re-read what i wrote. Initial is not syntesizable. Remove that block and replace it with the always block.

 

[funjoke]

just change that ?still got any problem on my code ?

 

[user_asic]

IDK. Still getting synthesis errors?

 

[funjoke]

$display($time, " rom32 error: unaligned address %d", address);
is that any problem with this sentence ?

 

[dilinx]

hi funjoke,
YES. "$display" is also not syntesizable....if u want it for simulation use sythesis directive "synthesis translate_off" and "synthesis translate_on"

 

[funjoke]

then in this question is use synthesis translate_on or translate_off?

 

[dilinx]

then in this question is use synthesis translate_on or translate_off?

for all "$display" and "initial" replace with synthesis translate off and on

for e.g.
//synthesis translate_off
$display($time, " rom32 error: unaligned address %d", address);
//synthesis translate_on

 

[funjoke]

$synthesis translate_off and translate_on($time, " rom32 error: unaligned address %d", address);


isnt what u mean by replace this ?

Added after 2 hours 10 minutes:

isnt change the display to synthesis translate_on


besides this is that any error that made this code non -synthesizable?

 

[dilinx]

isnt what u mean by replace this ?

Added after 2 hours 10 minutes:

isnt change the display to synthesis translate_on

sorry....yes u are right....change your code accordingly....
besides these, i think there is no synthesis error.....

 

[funjoke]

$synthesis translate_off and translate_on($time, " rom32 error: unaligned address %d", address);

u sure this line is correct by replacing this ?
what does synthesis translate_off and on means ?

 

[dilinx]

$synthesis translate_off and translate_on($time, " rom32 error: unaligned address %d", address);

u sure this line is correct by replacing this ?
what does synthesis translate_off and on means ?

the example i gave previosly....

or e.g.
//synthesis translate_off
$display($time, " rom32 error: unaligned address %d", address);
//synthesis translate_on

modify ur code like this for all "$display" statements.....

"//synthesis translate_off" and "//synthesis translate_on" are two constraints used to indicate XST or any other synthesis tool that anything between these two lines should not be synthesized and hence they are ignored by synthesis tool.....
These constraints are only for synthesizers not for simulators...hence simulator will treat these constraints as simple comment lines and ignore it.....

 

[funjoke]

initial begin
for (i=0; i<7; i=i+1) mem_array = i;
end

THIS PART NEED TO ADD A NOT ?

 

[dilinx]

initial begin
for (i=0; i<7; i=i+1) mem_array = i;
end

THIS PART NEED TO ADD A NOT ?

About initial bock, this depends on ur implementation.....if u want memory to be initialized on power up, use power-up reset and initialize to known values.....dont use initial.....

 

[funjoke]

//synthesis translate_off
$display($time, " rom32 error: unaligned address %d", address);
//synthesis translate_on

i feel this code have some problem on it ...i dun understand why need display ....can anybody helping in making this code more efficient

 

[pra]

Is there a testbench for this? If it has then you require this display statement for debug purpose... otherwise no use of it....

if you know C then display is just printf ... in real world there was no printing so thats why we use synsthesis translate off.
It's like ifdef in C. If you are running synthesis then it skip this else it executes this.

Hope you are clear now