shaiko
Advanced Member level 5
Hello,
A board I'm working on has an Altera Cyclone IV E FPGA with a single clock oscillator connected to one of the dedicated clock input pins. The device has 4 internal PLLs.
Can I use the single clock pin to drive more then one PLL (to generate several internal clocks)?
A board I'm working on has an Altera Cyclone IV E FPGA with a single clock oscillator connected to one of the dedicated clock input pins. The device has 4 internal PLLs.
Can I use the single clock pin to drive more then one PLL (to generate several internal clocks)?