Single clock input to multiple PLLs

[shaiko]

Hello,

A board I'm working on has an Altera Cyclone IV E FPGA with a single clock oscillator connected to one of the dedicated clock input pins. The device has 4 internal PLLs.

Can I use the single clock pin to drive more then one PLL (to generate several internal clocks)?

 

[FvM]

For Cyclone III and IV, a clock input can reach two PLLs directly and the other two through clock control blocks and global clock networks. The indirect connection involves slightly increased jitter.

 

[shaiko]

Just a thought...
If what I described is possible, why are there so many dedicated clock inputs to the device?

 

[ads-ee]

Just a thought...
If what I described is possible, why are there so many dedicated clock inputs to the device?

I haven't worked with Cyclone IV but at least in Cyclone III, a dedicated clock input on one side of the die can directly reach a PLL on that side of the die and an adjacent one on only one of the adjacent sides of the die. The adjacent input pin to PLL connection can't be compensated for so there will be increased jitter and skew in the output clocks. Going through clock control blocks and global clocks is not at all a direct connection to a PLL and the tools won't be able to compensate for clock input delays from the pin at all, therefore you would have to consider those clocks to be asynchronous to the clocks on the direct connections even if they are all at the same frequency.

In summary to allow direct connections to all PLLs you need clock input pins for each side of the die that has a PLL.

 

[shaiko]

ads-ee,

But it is possible to generate 2 completely different clocks from a single oscillator input...right?
For example, 50MHz and 32MHz from a single 100MHz input.

 

[ads-ee]

But it is possible to generate 2 completely different clocks from a single oscillator input...right?
For example, 50MHz and 32MHz from a single 100MHz input.

Yes, but only within the restrictions of the vco frequency that the PLL generates from the input clock and what the dividers can divide that vco frequency by.

So in the case of your example if the vco frequency is 800 MHz then to generate 50 MHz and 32 MHz outputs the output dividers would be 16 and 25 respectively.

 

[K-J]

Just a thought...
If what I described is possible, why are there so many dedicated clock inputs to the device?

What if you are processing several different processing or communications paths that are all independent and are already defined within a clock domain for each path? The clock for each path is an input to the processing logic, each clock might be the same frequency but maybe not in phase with any other and may have different drift or jitter characteristics in each channel. In that design instance, it is probably appropriate to process each path within the provided clock domain rather than to convert it into some other intermediate clock domain and then convert back to the original clock domain at the end. I'm not saying that this is a type of design that many people work with, but if happens to be a high volume application then it could be worth it to the FPGA suppliers to provide the capability. Just speculating.

Kevin Jennings