i use design compiler to synthesis, generate a netlist and SDF of a design written in verilog .. now wen tri to similute this file using model with sdf .. i get many errors saying tat many instances are missi..ports are missing and many more ..
Fatal: (vsim-SDF-3445) Failed to parse SDF file "design.sdf"
please soem let me know how can i simulate correctly ,.
Thanks lot for ur reply the following are the errors shown in the transcript ..
# ** Error: (vsim-SDF-3251) ***.sdf(82452): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82453): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82454): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82455): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82456): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82457): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82458): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82459): Failed to find port 'D'.
i am using a older version of model .. is it making any prob .. becuase . it also says .. fatel error in parsing ..
I did verror <errorcode> i got following info means
This is due to any of the following reason
1) There may be SDF syntax issue or The port may not be there in Entity or Module Defination ... Please check the same .
Try to ask your backend team whcih memory lib they used to generate SDF , try to goto that dir and pick the corresponding memory model that should solve the issue .
2) or IF you are annotation to wrong hierarchy too ....
Please let me know if you need any info ...
sim Message # 3251:
Either the specified port or the instance containing the port could
not be found in the design. Verify that the SDF file is being applied
at the correct level of the design.
[DOC: ModelSim User's Manual -
Standard Delay Format (SDF) Timing Annotation Chapter]
I am getting following error while simulating using SDF file.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(769): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(775): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(780): Module 'X_OPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(786): Module 'X_OBUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(791): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(797): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(802): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(808): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(814): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(827): Module 'X_SFF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(833): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(839): Module 'X_BUF' is not defined.