[SOLVED] Simulation error: module not found

[LatticeSemiconductor]

Hi there,

i have a problem with my vhdl testbench. i have an ip-core generated in verilog-code, wrapped and instantiated in my tb.
However, i get the following message in the simulator console:

"PUR_INST.PURNET" from module "tb.Inst_top.u1_dut.xjc8ae8.epa4aa7.baa8f3b" (module not found)

the core also includes a verilog testbench and macro-file for the simulation, which compiles fine

i am using the same macro, and i cannot seem to find any difference on how to instantiate the module between the verilog template and my vhdl code.

the missing module is required in ip-core_beh.v:

---

Code Verilog - [expand]
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`ifdef SGMII_NO_CTC
                yz29ae8  xjc8ae8 (  .rst_n (rst_n),  .mr_main_reset (tuda3da),  .thf96b3 (serdes_recovered_clk),  .ykcb59e (ofdce1f),  .vv5acf1 (wje70fc),  .end678f (nt387e4),  .oub3c7c (rx_clk_125),  .jr9e3e0 (psc5e98),  .hof1f06 (vk2f4c3),  .ir8f833 (ip7a61a),  .rg7c19c (rx_compensation_err)  );
assign ctc_drop_flag = 1'b0;
assign ctc_add_flag = 1'b0;

---

i beleave that ctc is set to dynamic (so it should, at least, although i cannot find its definition)

Any hints from your side? Surely this information is not enough to give any clues, but i dont know this much about verilog

 

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"PUR_INST.PURNET" from module "tb.Inst_top.u1_dut.xjc8ae8.epa4aa7.baa8f3b" (module not found)

This means the module (looks like PURNET) wasn't compiled prior to running the simulation.

Either the macro file has some extra stuff it's compiling that you didn't compile or there is a `include in the Verilog testbench.

 

[LatticeSemiconductor]

This means the module (looks like PURNET) wasn't compiled prior to running the simulation.

Either the macro file has some extra stuff it's compiling that you didn't compile or there is a `include in the Verilog testbench.

No `include in the verilog testbench.
I searched instantiation until tb.Inst_top.u1_dut.xjc8ae8, couldn't find any module from 'epa4aa7' on (which includes PURNET, presumably)

Since i could not find it, i think it is missing what could make sense to me since ifdef SGMII_NO_CTC should be false. I believe the condition WHEN this module is needed is not set correctly.

i haven´t checked if the instance contains any includes, going to do that tomorrow.

But i did search for SGMII_NO_CTC and could not find it?

Regarding compile order, i only call for Inst_beh.v in the macro file just like the example does
(components like 'xjc8ae8' are declared there) so the order should be correct.

The example also does not call any other files that could be missing here...

 

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Was the `define for SGMII_NO_CTC done in the original macro? That's usually where you find compile time defines that switch features on and off.

Can you post the macro that compiles and runs the Verilog simulation and your current script that runs the VHDL tb + Verilog UUT?

 

[LatticeSemiconductor]

Was the `define for SGMII_NO_CTC done in the original macro?

No, it's not

This is the example macro file:

---

Code ASM - [expand]
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cd "path/to/sim/aldec" 
workspace create sgmii_pcs_space 
design create sgmii_pcs_design . 
design open sgmii_pcs_design 
cd "path/to/sim/aldec" 
set sim_working_folder .
 
# compile the IP core ###############
vlog ../../src/SGMII_beh.v
 
# compile components ###############
vlog ../../src/register_interface_hb.v  
vlog ../../src/rate_resolution.v 
vlog ../../src/tx_reset_sm_sim.v 
vlog ../../src/rx_reset_sm_sim.v 
 
# compile top level hardware components ###############
vlog ../../../SGMII/src/pcs_serdes/pcs_serdes.v  
vlog ../../../SGMII/src/pmi_fifo_dc/pmi_fifo_dc.v  
 
# compile top level wrapper ###############
vcom ../../src/top_hb.vhd  
 
# compile testbench components of sgmii_node ###############
vlog ../../../SGMII/sim/tb/sgmii_node.v  
 
# compile testbench components of mii monitor ###############
vlog ../../../SGMII/sim/tb/port_parser_mii.v  
vlog ../../../SGMII/sim/tb/port_monitor.v  
vlog ../../../SGMII/sim/tb/mii_monitor.v  
 
# compile the testbench ###############
vlog ../../../SGMII/sim/tb/tb_hb.v 
 
#start the simulator
vsim +access +r -t 1ps -L pcsd_aldec_work -L ovi_ecp3 tb 
 
 
# list waves
view wave
onerror {resume}
add wave -divider {Control Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/rst_n
add wave -format Logic -radix hexadecimal sim:/tb/top/sgmii_mode
add wave -divider {Host Bus Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/hcs_n
add wave -format Logic -radix hexadecimal sim:/tb/top/hwrite_n
add wave -format Logic -radix hexadecimal sim:/tb/top/haddr
add wave -format Logic -radix hexadecimal sim:/tb/top/hdatain
add wave -format Logic -radix hexadecimal sim:/tb/top/hdataout
add wave -format Logic -radix hexadecimal sim:/tb/top/hready_n
add wave -divider {(G)MII Inbound Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_source
add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_sink
add wave -format Logic -radix hexadecimal sim:/tb/top/en_in_mii
add wave -format Literal -radix hexadecimal sim:/tb/top/data_in_mii
add wave -format Logic -radix hexadecimal sim:/tb/top/err_in_mii
add wave -divider {(G)MII Outbound Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_source
add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_sink
add wave -format Logic -radix hexadecimal sim:/tb/top/dv_out_mii
add wave -format Literal -radix hexadecimal sim:/tb/top/data_out_mii
add wave -format Logic -radix hexadecimal sim:/tb/top/err_out_mii
add wave -format Logic -radix hexadecimal sim:/tb/top/col_out_mii
add wave -format Logic -radix hexadecimal sim:/tb/top/crs_out_mii
add wave -divider {SERDES Outbound Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutp0
add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutn0
add wave -divider {SERDES Inbound Signals}
add wave -format Logic -radix hexadecimal sim:/tb/top/hdinp0
add wave -format Logic -radix hexadecimal sim:/tb/top/hdinn0
 
 
# run simulation cycles
run -all

---

For a simple test, i even wrapped all components in VHDL and used the macro file as it is but the testbench...

---

Code ASM - [expand]
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[...]
# compile the testbench ###############
# vlog ../../../SGMII/sim/tb/tb_hb.v 
vcom ../../../SGMII/sim/tb/tb_hb.vhd 
 
[...]

---

One thing i am not sure about:

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Code Verilog - [expand]
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// G/MII Interface
   .data_in_mii ( {local_tx_d} ) ,
   .en_in_mii ( local_tx_en ) ,
   .err_in_mii ( local_tx_er ) ,

---

.data_in_mii ( {local_tx_d} ) , => Is this the concatenation of a single signal? i dont see what { } is making any difference on beeing there...

- - - Updated - - -

OK, there were 2 primitives missing in my testbench, GSR and PUR. It is working now.

 

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OK, there were 2 primitives missing in my testbench, GSR and PUR. It is working now.

Does this mean you forgot to complie glbl.v?

 

[LatticeSemiconductor]

No, there where two instantiations in the verilog testbench:

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Code Verilog - [expand]
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GSR GSR_INST    (.GSR(rst_n));
PUR PUR_INST    (.PUR(1'b1));

---

For the simulation to work properly, i have to add Global Set / Reset and Power Up Set / Reset primitives, they are needed for the ip-core.

In my VHDL i ignored them since they are not connected to anywhere (they have only inputs, no outputs - the simulator then adds connections automatically).
Once i added them i got rid of the error message.

- - - Updated - - -

Does this mean you forgot to complie glbl.v?

hm, yes looks like glbl.v does the same

 

[LatticeSemiconductor]

Just for curiosity - do you know how to compile these components (GSR, PUR, etc) without explicitely calling them?
I added them in my macro file (vlog .../gsr.v), so it works but ... the example does not.

the component source files are located under <install_dir>/../ovi_ecp3/ and i also use 'ovi_ecp3' in my 'vsim' command but no difference
no include in the verilog files as well