Simulation and synthesis.

[harshahari]

I have mentor tools for simulation and synthesis the verilog code in that tools i i have got some errors while run the code those are token 'ifndef' was not defined and no 'ifndef' was not found to match 'endif'. and now tell me what is the meaning of 'ifnedf' and how to correct the these errors?

 

[ThisIsNotSam]

these are called directives. they are present in many programming languages, there is nothing special about them. just inspect the code and look for them. this is a trivial exercise.

 

[harshahari]

Yaa ok but while synthesis the code the errors are occurred then how can i correct these errors.

 

[harshahari]

Yaa ok now my question is if we synthesis the code with directives then we got errors and if we delete the those directives ('ifndef,ifdef) fromcode then becoming output is correct or not?

 

[slutarius]

`ifdef, `ifndef, `elsif, `else and `endif conditionally compiles Verilog code, depending on whether or not a specified macro is defined. Any code that is not compiled must still be valid Verilog code.

Link by doing Google search with keywords: "`ifndef Verilog"

https://www.hdlworks.com/hdl_corner/verilog_ref/items/CompilerDirectives.htm