[SOLVED] Simulation Accuracy in veriloga (hspice) for very low jitter

[neoflash]

Hi guys,

I met one challenge in simulating the low jitter synthesizer in verilogA in hspice simulator.

The theoretical rms jitter of the synthesizer is expected to be a few hundred fs. However, the accuracy of the simulator is somehow limited to be at ps level.

How can I further improve the simulation accuracy for this verification in hspice?

Thanks,
Neo

 

[prcken]

as i know the absolute resolution of hspice defines the resolution of the simulator, you can check the default value to see whether it meet your accuracy, and also you can change it in the .option in terms of hspice.
i suggest you go to check the hspice manual for details.