Simulating VHDL code with R-L load

[shrinivas.gotur]

---

Code VHDL - [expand]
1
2
3
4
Hi guys, 
 I have this VHDL Code which is perfectly simulating in Modelsim with dummy load, but now i want to use real R-L load ,so i am thinking to import  vhdl code to orcad and connect the load to the code and simulate it into Pspice Please tell me how to do this.????
 Thanks in advance
:???::thinker:

---

 

[TrickyDicky]

VHDL is a digital HDL, and not really for analogue applications. Have you looked into VHDL-AMS instead?

 

[rajavel.rv]

VHDL is a digital HDL, and not really for analogue applications. Have you looked into VHDL-AMS instead?

if its possible to do this in verilog hdl; if its possible means how can i design this type of analog hardware in verilog code and please post which book material or link was good reference for me.

ref : **broken link removed**

regards
rajavel.rv

 

[TrickyDicky]

That is Verilog-AMS.

- - - Updated - - -

both -AMS languages are meant for modelling only - you cannot synthesise hardware from them.