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Simulating Verilog Functional code in Virtuoso ADE

Thread starter Wheatley
Start date Nov 22, 2017

Status: Not open for further replies.

Nov 22, 2017

#1

W

Wheatley

Junior Member level 2

Hi,

Is it possible to simulate Verilog Functional code (not compiled) in Virtuoso ADE?

Thanks in advanced!

Status: Not open for further replies.

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