LatticeSemiconductor
Member level 2
Hi,
on my simulation i can observe a buffer overflow in my dual port fifo due to the writing bandwidth beeing 0.0223 % larger than the reading bandwidth. The writing clock is 6 times faster than the read clock, the write enabled for every 6th clock and the read always enabled.
The error is caused by the reference clock i set for the PLL, which is generating read and write clocks. The reference clock should be 55.6875 MHz, but in my testbench i can only specify clock periods in ps so i cannot set this exact frequency in the testbench.
How can i create such frequency for my testbench?
i read in a forum that one could use several time periods to obtain, in average, high and low time period of the desired frequency.
the problem is that i need the exact frequency for my fifo never to underflow or overflow. Is there a way to do that?
thanks
on my simulation i can observe a buffer overflow in my dual port fifo due to the writing bandwidth beeing 0.0223 % larger than the reading bandwidth. The writing clock is 6 times faster than the read clock, the write enabled for every 6th clock and the read always enabled.
The error is caused by the reference clock i set for the PLL, which is generating read and write clocks. The reference clock should be 55.6875 MHz, but in my testbench i can only specify clock periods in ps so i cannot set this exact frequency in the testbench.
How can i create such frequency for my testbench?
i read in a forum that one could use several time periods to obtain, in average, high and low time period of the desired frequency.
the problem is that i need the exact frequency for my fifo never to underflow or overflow. Is there a way to do that?
thanks