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Simple verilog compiling question about includes

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tomaccogoats

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I'm using ncverilog and i'm curious if there's a way I can force an include on all my files. Say I have a directory full of files that need to compiled, and they all require a defines file. Is there some compile option to force the defines to be processed before trying to compile everything else, so that I don't have to go into every file and paste in the "include" line?

Also is there a way to compile based on what's needed? Like if a top level module is needs other modules to be compiled, can it recognize that and compile the lower level modules first, or would I just make a Makefile for that?
 

yx.yang

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I'm using ncverilog and i'm curious if there's a way I can force an include on all my files. Say I have a directory full of files that need to compiled, and they all require a defines file. Is there some compile option to force the defines to be processed before trying to compile everything else, so that I don't have to go into every file and paste in the "include" line?

Also is there a way to compile based on what's needed? Like if a top level module is needs other modules to be compiled, can it recognize that and compile the lower level modules first, or would I just make a Makefile for that?
Hi, For the "include" file problem: you have some choice:
1): Add `include "include.file_name" in each of the RTL files you need these inlcude define or parameters.
2): If there is just some defines in the include files, you can choose to use ncverilog option "+define+" to define them one by one in ncverilog command line.
3): You can generate a file list first and put the include file in the first line (or line before the first RTL code need the defines or parameters). A file list will save you a lot of time at sim/debussy/DC compile.

For the compile and recognize top level module problem, there is no need by ncverilog to compiler top level module first. While it's a way to compile the top level file first.

At last, you'd better use "ncverilog -help" command to get more info.
 

kulkarni_saurabh

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Not sure about the exact syntax for NCVerilog. In ModelSim the switch to be included at command line goes like this:
Code:
+incdir+directory_for_include_files
There should be a similar switch for NCVerilog, if not the same one.

You will have to use:
Code:
`include "my_include_file.v"
In every file you use those constants.

Hope this helps.

Regards,
Saurabh
 

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