[SOLVED] Simple Spartan-3E program simulates well but wont run in hardware....

[casiocalcs]

Hi, This is my first post!
I am really new to the world of FPGA and am trying to educate myself from a FPGA prototyping textbook, but came unstuck with one of the early experiments.

The Verilog program is a 2-to-4 binary decoder. The UCF is below. I added the "indicator" signal because I was trying to determine if the enable button is working in hardware.
When the program is loaded to the FPGA, I get no LEDs (LED0-LED3) whatsoever ( I do have the normal power, USB and system LEDs).

I presume that there is a design flaw in my code or UCF. Any constructive advice would be greatly appreciated.

[syntax=verilog]
module two_2_four(
    input [1:0] in2,
	 input enable,
    output [3:0] out2,
	 output indicator
    );

//internal signals
wire d0,d1,d2,d3;
wire [3:0] enab;

//body
assign out2 = enab & {d3, d2, d1, d0};

//product terms
assign d0 = (~in2[1] & ~in2[0]);
assign d1 = (~in2[1] & in2[0]);
assign d2 = (in2[1] & ~in2[0]);
assign d3 = (in2[1] & in2[0]);
//misc
assign enab = {enable, enable, enable, enable};
assign indicator = enable;

endmodule
[/syntax]

-------------------------------------

[syntax=verilog]

# Slide switches
NET "in2<0>" LOC = "L13";	#SW0
NET "in2<1>" LOC = "L14";	#SW1

#From Starter-3E user guide
NET "enable" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; # Btn West

# LEDs
NET "indicator" LOC = "F9"; 	#LED7

#Format from Starter-3E user guide
NET "out2<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 		#LED3
NET "out2<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 		#LED2
NET "out2<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 		#LED1
NET "out2<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = ;8 		#LED0




[/syntax]

 

[barry]

Are you mapping the pins to the correct devices on your dev board?

 

[casiocalcs]

Are you mapping the pins to the correct devices on your dev board?

Hi Barry,
Yes, I have used this UCF file for the previous experiment (almost identical). I have triple checked the resource references (e.g. SW0 = L13) and they are correct.

I even tried setting

assign indicator = 1;

in my verilog file just to make one of the LEDs come on. Still no luck.

 

[barry]

I don't know Verilog, sorry I can't help with your code.

 

[joelby]

Do you get any warnings during synthesis?

 

[mrflibble]

Well, I would expect a big fat error, what with line 15 of the UCF file. This bit: "DRIVE = ;8"

I would expect an assign of 1 or 0 to the led IO's gets you a result. Double check the IO report to see if you really get outputs where you expect. Or one step lower level, open your design in fpga editor and see what is connected to the IOB.

Having said that, are you absolutely certain you are using the right fpga pins? As in, do you have 1 other design that uses the same UCF and is actually blinking some leds? Most likely error is something in the UCF. The verilog seems okay. Oh and be sure to check both options of 1 and 0 for your assign indicator... Just in case of some silly inversion somewhere.

What dev board are you using?

 

[casiocalcs]

Hi mrflibble,

You are correct, that would be a big fat error. At the time of writing my last I was making lots of attempts with slight variations of my code, and the one I posted happened to be syntactically broken. However, I fixed that error with no improvement in my result. I like the idea of possible 'asserted low' logic for the LEDs, but it aslo didn't help in either 0 or 1 case. I have also tried lots of combinations in the UCF, and the verilog assignment of 'indicator' especially, (inluding assign to 0, 1 and 'enable').

I have used this (almost identical) UCF in another project that built and ran well in hardware. I have a Spartan 3E Starter kit.

Okay, I just checked the FPGA editor (which I have never used before and find somewhat difficult to use). The pane called 'List1' has my 'components' (inputs and outputs) as well as a 'site' for them. In my earlier project the 'site' field matched the UCF, but in this one it doesn't. Seems likely to be the problem. How do I fix it????

Thanks for your previous advice,
CC

Well, I would expect a big fat error, what with line 15 of the UCF file. This bit: "DRIVE = ;8"

I would expect an assign of 1 or 0 to the led IO's gets you a result. Double check the IO report to see if you really get outputs where you expect. Or one step lower level, open your design in fpga editor and see what is connected to the IOB.
(snip)

What dev board are you using?

- - - Updated - - -

Hi Joelby,

I mentioned in my last post, at the time of writing my last I was making lots of attempts to find the problem, using slight variations of my code. Most of them 'compiled' fine. It turns out that somehow the Programming File Generator is not getting the right resources from the UCF. No idea why not at this point in time.

 

[casiocalcs]

All fixed.

I found I had accidently introduced a new, blank UCF into my project at some point, which was associated with the top level module. The resource placement was therefore arbitrarily chosen it seems. The UCF file I posted and was editing was totally irrelevant it seems.

Big thanks to all who posted (and viewed) responses, ultimately led me to find my mistake.
Cheers,
CC

Btw the FPGA editor is still baffling me, and any brief guide would be very welcome

 

[mrflibble]

Yup, using the wrong UCF will definitely mess things up. ;-)

To check your IO pins you can also view the IOB Properties and Pinout Report in the Design Summary.

Check this for a tutorial on fpga editor:
https://www.youtube.com/watch?v=wwkGmDaa4oM
https://www.youtube.com/watch?v=GYLi098O7uM
https://www.youtube.com/watch?v=kSrOvem7pEU