Verilog functions are used to save typing, and can't contain any timing statements (i.e. #, fork-join, etc), but they can contain if-else statements. Consult the Language Reference Manual to see for yourself.
Functions are placed inside of always blocks, so I am not sure why arishsu was concerned that they fell outside of them.
I forgot to add that I currently am using many functions that contain if-else statements in my current project and they simulate and synthesize just fine.
r.b.