[SOLVED] simple question: using verilog can one have an if statment inside a function?

[aelbad]

I just wanted to know if it is not a problem using an if statement inside a function to assign a value to the function output (this should be a simple question )

 

[arishsu]

I just wanted to know if it is not a problem using an if statement inside a function to assign a value to the function output (this should be a simple question )

Which programming language? If you are talking about verilog, you can't use if statement outside always loop. You can use conditional operator to assign a value to a variable outside always loop.

 

[rberek]

Verilog functions may contain if-else statements.

r.b.

 

[aelbad]

Which programming language? If you are talking about verilog, you can't use if statement outside always loop. You can use conditional operator to assign a value to a variable outside always loop.

I am talking about verilog. but still one can use an if statement inside a task as well then why not inside a function?

now we have two contradictory replies by arishsu and rberek :thinker:

 

[TrickyDicky]

It would be very odd not to be able to use if-else statements in a function. But whether it is synthesisable depends on the function behaviour.

 

[rberek]

Verilog functions are used to save typing, and can't contain any timing statements (i.e. #, fork-join, etc), but they can contain if-else statements. Consult the Language Reference Manual to see for yourself.

Functions are placed inside of always blocks, so I am not sure why arishsu was concerned that they fell outside of them.

I forgot to add that I currently am using many functions that contain if-else statements in my current project and they simulate and synthesize just fine.

r.b.

 

[arishsu]

now we have two contradictory replies by arishsu and rberek :thinker:

I never mentioned function anywhere. In fact I didn't notice that 'function' word. Sorry for the mistake.

Functions are placed inside of always blocks, so I am not sure why arishsu was concerned that they fell outside of them.
r.b.

Completely agree with that.

 

[ads-ee]

now we have two contradictory replies by arishsu and rberek

Because unlike rberek, arishsu hasn't been using Verilog at work for years. Hence the contradictory replies...one from an experienced Verolog coder and one from presumably a student based on their previous posts.

 

[aelbad]

Thank you everyone for your helpful quick support, I really appreciate it.:thumbsup: