BartlebyScrivener
Member level 5
I am trying to write a 5 input round robin arbiter. It appears to work in isolation, but when used in my network it seems to be failing me.
It is hard for me to find when it is failing in the network due to complexity, but when I use a different fixed priority arbiter module I wrote that I know works in my network, the network drops no packets, but when using the round robin arbiter It drops approx 1% of packets. Can anyone see why from this code?
I really can't see anything wrong with the actual code/logic I have checked it loads and it seems simple, but then perhaps I am blinded from something simple!
The cell I made is ...
---------- Post added at 16:59 ---------- Previous post was at 16:55 ----------
Does Modelsim SystemVerilog get confused by the wrap around? Is it program confusion as appose to programming confusion? This has been rattling my head all day, I have rewritten it so many times!
It is hard for me to find when it is failing in the network due to complexity, but when I use a different fixed priority arbiter module I wrote that I know works in my network, the network drops no packets, but when using the round robin arbiter It drops approx 1% of packets. Can anyone see why from this code?
I really can't see anything wrong with the actual code/logic I have checked it loads and it seems simple, but then perhaps I am blinded from something simple!
Code:
module arbiter
// The amount of lines to arbitrate is passed as a parameter, the default being 5.
#(parameter n = 5)
// The arbiter outputs a one-hot n bit word denoting the port request that has been granted from
// the port requests inputted in a one-hot fashion.
(output logic [n-1:0] portGrant,
input logic [n-1:0] portRequest,
input logic reset, clk);
// Internal logic for priority and carry bits.
logic [n-1:0] portPriority;
logic [n-1:0] carryBit;
// Combinational logic describing an n-bit variable priority iterative arbiter. This logic
// should be able to be used with different schemes to generate the one-hot priority input but this didnt work
// so I commented it out and tried making individual arbiter cells and instantiating them below.
/*
always_comb
begin
for (int i=0; i<n; i++)
begin
portGrant[i] = (portRequest[i] && ( carryBit[i] || portPriority[i] ));
carryBit[i+1] = (!portRequest[i] && ( carryBit[i] || portPriority[i] ));
end
carryBit[0] = carryBit[n];
end
*/
variablePriorityArbiter arbite0 (portGrant[0], carryBit[1], portPriority[0], portRequest[0], carryBit[0]);
variablePriorityArbiter arbite1 (portGrant[1], carryBit[2], portPriority[1], portRequest[1], carryBit[1]);
variablePriorityArbiter arbite2 (portGrant[2], carryBit[3], portPriority[2], portRequest[2], carryBit[2]);
variablePriorityArbiter arbite3 (portGrant[3], carryBit[4], portPriority[3], portRequest[3], carryBit[3]);
variablePriorityArbiter arbite4 (portGrant[4], carryBit[0], portPriority[4], portRequest[4], carryBit[4]);
// Priority input generation.
always_ff @ (posedge clk)
begin
if (reset)
portPriority <= 'b00001;
else
begin
// Round Robin
portPriority <= |portGrant ? {portGrant[n-2:0], portGrant[n-1]} : portPriority;
end
end
endmodule
The cell I made is ...
Code:
module variablePriorityArbiter
(output logic G, Cout,
input logic P, R, Cin);
logic a;
or gate1 (a, Cin, P);
and gate2 (G, R, a), gate3 (Cout, a, ~R);
endmodule
---------- Post added at 16:59 ---------- Previous post was at 16:55 ----------
Does Modelsim SystemVerilog get confused by the wrap around? Is it program confusion as appose to programming confusion? This has been rattling my head all day, I have rewritten it so many times!