Significance of " MOS transistor Ring structure"

[ninge]

ring mos structure

Hi All!!!

Anyone explain me about Significance of " MOS transistor Ring structure" in Layout ( I mean ploy gate drawn in ring structure) and its Advantages...particularly in which condition that type of structure is preferred....

Thanks,
Ninge

 

[chenjia]

nimp, layout, bulk, nmos

Can useage of the area be more efficeincy?

 

[manish12]

geomenclosure

not preferable MOS structure !


becose, D/S area is not balance / not equal here ! , it may be the reason ,

 

[engrak]

ring transistor

such type of enclosed transistor is used for Radiation hard devices .

 

[kola]

mos,inner gate resistor

such type of enclosed transistor is used for Radiation hard devices .

exactly

 

[277897909]

star-rcxt dspf tcad_grd_file

such type of enclosed transistor is used for Radiation hard devices .

What is a Radiation hard device?
So far as I know,to use such ring structure of mos transistors effectively minimize the Cgd,if it the inner region is connected as drain.

 

[n1cm0c]

significance of transistor

Enclosed geometry nmos transistors are used to reduce the leakage current from drain to source that appears after exposure to ionizing radiation.

This layout also has the advantage that the inner part (usually connected as the drain) has much lower capacitance than the outer one (usually connected as the source). This kind of layout is not very useful for general design because it's not accurately modeled by any circuit simulator. Another disadvantage is that it's impossible to obtain W/L ratios less than ~2, and the W/L ratio is poorly defined anyhow.

A similar technique is the waffle layout , which is very useful for low noise amplifiers, and it also helps for radiation hardness.

 

[Yarrow]

ad as pd pf mos physical parameters

I am currently trying to implement the enclosed layout transistor (ELT )into a RHBD latch to improve the robustness.

If I am not mistaken the ELT is supposed to provide higher gain in addition to reduced leakage current compared with the standard MOSFET layout.

Has anyone had any success with simulating the leakage current of the ELT (and confirming the theory)??

I simulated the leakage current post layout, and actually got a 2.5x increase in leakage current!!! I am using Cadence Vertouso. I am not sure the the simulator can handle the layout accurately, as n1mc0c mentioned. I will go over the extracted parameters and check out what really has been extracted compared to the intenden dimentions.

If anyone has any experience with working with ELTs, all input is appriciated!

 

[Yarrow]

ring type transistor

Ok I took a look at the extracted parameters:

//
simulator lang=spectre insensitive=yes
// |DSPF 1.3
// |DESIGN elt
// |DATE "Thu Mar 12 15:59:41 2009"
// |VENDOR "Synopsys"
// |PROGRAM "Star-RCXT"
// |VERSION "Z-2007.06-SP1 "
// |DIVIDER /
// |DELIMITER :
// FORMAT NETNAME
//

// COMMENTS

// TCAD_GRD_FILE /ifi/midgard/h01/amirh/Cadence/plsimulation/Fun-elt-schematic/Fun-elt-layout/phase1/pls1/initDir/RCMAX.nxtgrd
// TCAD_TIME_STAMP Wed Sep 21 13:32:50 2005
// TCADGRD_VERSION 43


subckt elt_pls_rcmax_rcc ( 0 vdd! vg )

// |GROUND_NET 0

// |NET vg 0.0006001PF
// |P (vg O 0 12.68 37.14)
// |I (vg:F9 MM0 G I 0.00320845 12.24 34.6)
// |S (vg:F5 12.68 37.14)
rxvg ( vg vg\:f5 ) resistor r=0.001
cg1 ( vg\:f5 0 ) capacitor c=1.28785e-17
cg2 ( vg\:f9 0 ) capacitor c=3.41647e-17
r1 ( vg\:f5 vg\:f9 ) resistor r=66.95

// |NET 0 0.000698462PF
// |I (0 MM0 B B 0 12.24 34.6)
// |P (0 O 0 13.41 31.25)
// |I (0 MM0 S B 0 12.24 34.6)
// |S (0 13.41 31.25)
rx0 ( 0 0 ) resistor r=0.001
c3 ( 0 vg\:f5 ) capacitor c=2.37485e-16
cg4 ( 0 0 ) capacitor c=9.5926e-19
c5 ( 0 vg\:f9 ) capacitor c=1.84934e-16
c6 ( 0 vg\:f5 ) capacitor c=1.45384e-18
cg7 ( 0 0 ) capacitor c=7.20677e-17
c8 ( 0 vg\:f5 ) capacitor c=2.08887e-17
c9 ( 0 vg\:f9 ) capacitor c=4.23945e-17
cg10 ( 0 0 ) capacitor c=5.60999e-17
r2 ( 0 0 ) resistor r=3.64282
r3 ( 0 0 ) resistor r=1.30008

// |NET vdd! 0.000152619PF
// |P (vdd! O 0 13.31 34.17)
// |I (vdd:F8 MM0 D B 0 12.64 34.1)
// |S (vdd:F4 13.31 34.17)
rxvdd! ( vdd! vdd\:f4 ) resistor r=0.001
c11 ( vdd\:f4 0 ) capacitor c=4.17297e-17
c12 ( vdd\:f4 vg\:f5 ) capacitor c=2.07607e-19
c13 ( vdd\:f4 vg\:f9 ) capacitor c=6.56935e-17
c14 ( vdd\:f4 0 ) capacitor c=2.47333e-17
c15 ( vdd\:f4 0 ) capacitor c=8.18716e-18
cg16 ( vdd\:f4 0 ) capacitor c=4.25478e-18
c17 ( vdd\:f8 0 ) capacitor c=2.14225e-19
c18 ( vdd\:f8 0 ) capacitor c=7.31515e-18
cg19 ( vdd\:f8 0 ) capacitor c=2.83446e-19
r4 ( vdd\:f4 vdd\:f8 ) resistor r=8.76756

//
// Instance Section
//
xmm0 ( vdd\:f8 vg\:f9 0 0 ) nsvt ad=2.6861 as=7.19295 l=0.437621 pd=0u
+ ps=11.4607 w=7.33158 po2act=7.33158

ends elt_pls_rcmax_rcc



I dont know what these parameters stand for:
ad
as
pd
ps
po2act

Anyone have any idea on what these parameters mean?

 

[Blackuni]

fem mos transistor

Hi,

refer any book on analog design, ken martin, baker..
ad --> drain area
as --> source area
pd --> perimeter of drain
ps --> perimeter of source

Last 1 i dono

Thanks,

 

[Yarrow]

mos ring on ring contact structure

Tnx Blackuni

I just got to working with this again today. The po2act is the distance from the poly gate to the active region end it seems.

Anyways, I measured the parameters and compared them to the extracted layout parameters, and the extracted parameters were totaly wrong. for example the "drain area" was extracted as 50% bigger then the actual dimensions in the layout. The extracted parameters are a total mess, and a huge bummer

Does anyone know where to input the right parameter values so that the correct extract can be made?

 

[erikl]

ring transistors

The po2act is the distance from the poly gate to the active region end it seems.

Not the distance. I think po2act is the perimeter of the poly gate, as it is identical to the gate width w .

Does anyone know where to input the right parameter values so that the correct extract can be made?

If you trust your "manual" extraction better than the extraction tool's result, why not change the extracted netlist manually to your results and repeat your simulation(s)?

 

[sdedov]

significances of mos

Tnx Blackuni

I just got to working with this again today. The po2act is the distance from the poly gate to the active region end it seems.

Anyways, I measured the parameters and compared them to the extracted layout parameters, and the extracted parameters were totaly wrong. for example the "drain area" was extracted as 50% bigger then the actual dimensions in the layout. The extracted parameters are a total mess, and a huge bummer

Does anyone know where to input the right parameter values so that the correct extract can be made?

Everything is up to extraction rules. Im not an expert in STAR, but as for Assura/Calibre, one needs to take into account multibent/ring transistor
structures if writing rules...
Pay you attention that the drain area is 0...

BTW, as for leakage current, most of new technologies uses LDD technique and for ring transistors some fabs does guarantee higher leakage. And unfortunately it could not be considered with any 2D extraction tools

 

[Yarrow]

dspf 1.3

If you trust your "manual" extraction better than the extraction tool's result, why not change the extracted netlist manually to your results and repeat your simulation(s)?

Thats the thing, editiong the extracted netlist would be a major task, and I dont trust myself enough to calculate all the capacitances and resistances correctly.

What I was hoping for was to edit the file the extraction tool bases its extraction on. In that way I could just change the dimensions with the manually measured dimensions and hopefully get better extracted results based on the new correct transistor dimensions. The problem is, I dont know where that file is.

Pay you attention that the drain area is 0...

The extracted drain are is (ad=) 2.6861 in that perticular case. But when measured manually, its about 50% smaller. The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

As for the writing extraction rules, that is outside my knowlage. Perhaps that is the way to go if I want to get any results within a reasonoble scope. Tnx for the info, i will look into it.

 

[erikl]

waffle geometry transistors

What I was hoping for was to edit the file the extraction tool bases its extraction on. In that way I could just change the dimensions with the manually measured dimensions and hopefully get better extracted results based on the new correct transistor dimensions. The problem is, I dont know where that file is.

Search in your extraction setUp. At Cadence, it is usually called assuraEXT.rul or divaEXT.rul (depending on which extraction tool you use).
This is, however, a relatively complex file, s. the following (old) example from a Cadence tutorial (below).

/*************************************************************************

Title: Assura Extract rules for GENERIC PDK, Version 4.4.6 Process
Library Specification No. GPDK446, Version 1.0


Notes: Cadence Design Systems, Inc.
PDK TECHNOLOGY CENTER, Melbourne, FL
March 15, 2001


LEGAL STUFF
_____________________________________________________________________
* Cadence Design Systems shall not be liable for the accuracy of *
* this design rule deck or it's ability to capture errors. The user *
* is responsible for thoroughly testing and implementing it's *
* features. *
*---------------------------------------------------------------------*


Revision History:

04/24/01 Added Metal4, Metal5 & Metal6

03/15/01 First Customer Release, Version 1.0


*************************************************************************/

drcExtractRules(

ivIf( (switch "extract?") then

layerDefs( "df2"

Nwell = layer( "Nwell" )
Nburied = layer( "Nburied" )
Pwell = layer( "Pwell" )
Oxide = layer( "Oxide" )
Poly = layer( "Poly" )
Pimp = layer( "Pimp" )
Nimp = layer( "Nimp" )
Cont = layer( "Cont" )
Metal1 = layer( "Metal1" )
Via1 = layer( "Via1" )
Metal2 = layer( "Metal2" )
Via2 = layer( "Via2" )
Metal3 = layer( "Metal3" )
Via3 = layer( "Via3" )
Metal4 = layer( "Metal4" )
Via4 = layer( "Via4" )
Metal5 = layer( "Metal5" )
Via5 = layer( "Via5" )
Metal6 = layer( "Metal6" )
CapMetal = layer( "CapMetal" )
Capdum = layer( "Capdum" )
Resdum = layer( "Resdum" )
BJTdum = layer( "BJTdum" )
NPNdummy = layer( "NPNdummy" )
PNPdummy = layer( "PNPdummy" )
IND2dummy = layer( "IND2dummy" )
INDdummy = layer( "INDdummy" )
DIOdummy = layer( "DIOdummy" )
text = layer( "text" )

mt1_text = textToPin( "Metal1" )
mt2_text = textToPin( "Metal2" )
mt3_text = textToPin( "Metal3" )
mt4_text = textToPin( "Metal4" )
mt5_text = textToPin( "Metal5" )
mt6_text = textToPin( "Metal6" )

)

layerDefs( "gds2"

Nwell = layer( 2 )
Nburied = layer( 19 )
Pwell = layer( 18 )
Oxide = layer( 1 )
Poly = layer( 3 )
Pimp = layer( 5 )
Nimp = layer( 4 )
Cont = layer( 6 )
Metal1 = layer( 7 )
Via1 = layer( 8 )
Metal2 = layer( 9 )
Via2 = layer( 10 )
Metal3 = layer( 11 )
Via3 = layer( 30 )
Metal4 = layer( 31 )
Via4 = layer( 32 )
Metal5 = layer( 33 )
Via5 = layer( 34 )
Metal6 = layer( 35 )
CapMetal = layer( 14 )
Capdum = layer( 12 )
Resdum = layer( 13 )
BJTdum = layer( 15 )
NPNdummy = layer( 20 )
PNPdummy = layer( 21 )
DIOdummy = layer( 22 )
IND2dummy = layer( 17 )
INDdummy = layer( 16 )
text = layer( 60 )

mt1_text = textToPin( 7 )
mt2_text = textToPin( 9 )
mt3_text = textToPin( 11 )
mt4_text = textToPin( 31 )
mt5_text = textToPin( 33 )
mt6_text = textToPin( 35 )

)


/* Derive Substrate */

bulk = geomBkgnd()
Psub = geomAndNot( bulk geomOr( Nwell Nburied) )


/* MOS derivations */

NPOD = geomAnd( Nimp Oxide )
ntox = geomAnd( NPOD Psub )
ngate = geomAndNot( geomAnd( ntox Poly ) Capdum )
ndiff = geomAndNot( ntox ngate )
ntie = geomAnd( NPOD Nwell )
nmos = geomOr( ngate )

PPOD = geomAnd(Pimp Oxide)
ptox = geomAnd( PPOD Nwell )
pgate = geomAndNot( geomAnd( ptox Poly ) Capdum )
pdiff = geomAndNot( ptox pgate )
ptie = geomAnd( PPOD Psub )
pmos = geomOr( pgate )


/* poly resistor derivations */
polyres = geomAnd( Poly Resdum )
Poly = geomAndNot( Poly polyres )


/* diffusion resistor derivations */
nplusres = geomAnd( ntox Resdum )
ndiff = geomAndNot( ndiff nplusres )


/* MOS capacitor derivations */
nmoscap = geomAnd( geomAnd( ntox Capdum ) Poly )
ndiff = geomAndNot( ndiff nmoscap )

nmoscapm1 = geomAnd( Metal1 geomEnclose( geomSize( NPOD .6 ) geomAnd( Poly Capdum ) ) )
Metal1 = geomAndNot( Metal1 nmoscapm1 )
nmoscapm2 = geomAnd( Metal2 geomEnclose( geomSize( NPOD .6 ) geomAnd( Poly Capdum ) ) )
Metal2 = geomAndNot( Metal2 nmoscapm2 )

m1MoscapConnector = geomAnd( geomSize( Metal1 .01) geomSize( nmoscapm1 .01 ) )
m1MoscapCont = geomAnd( Metal1 m1MoscapConnector )
Moscapm1Cont = geomAnd( nmoscapm1 m1MoscapConnector )

m2MoscapConnector = geomAnd( geomSize( Metal2 .01) geomSize( nmoscapm2 .01 ) )
m2MoscapCont = geomAnd( Metal2 m2MoscapConnector )
Moscapm2Cont = geomAnd( nmoscapm2 m2MoscapConnector )

/* metal capacitor derivations */
mimcap = geomAnd( Capdum CapMetal )
capm2 = geomAnd( Metal2 Capdum )
capm3 = geomAnd( Metal3 Capdum )
capv23 = geomAnd( Via2 CapMetal )
Via2 = geomAndNot( Via2 capv23 )

;Need to separate out metalInterconnect for parasitic extraction purposes.
;(don't want to extract parasitic c on mim capacitor)
Metal2 = geomAndNot( Metal2 capm2 )
m2IntCapConnector = geomAnd( geomSize( Metal2 .01) geomSize( capm2 .01 ) )
m2IntCapCont = geomAnd( Metal2 m2IntCapConnector )
capm2Cont = geomAnd( capm2 m2IntCapConnector )
Metal3 = geomAndNot( Metal3 capm3 )
m3IntCapConnector = geomAnd( geomSize( Metal3 .01) geomSize( capm3 .01 ) )
m3IntCapCont = geomAnd( Metal3 m3IntCapConnector )
capm3Cont = geomAnd( capm3 m3IntCapConnector )


/* diode derivations */
pdiodePlus = geomAnd( DIOdummy ptox )
pdiode = geomEnclose( DIOdummy pdiodePlus )
ndiodeMinus = geomAnd( DIOdummy ntox )
ndiode = geomEnclose( DIOdummy ndiodeMinus )


/* vertical pnp derivation */
vpnpBase = geomAnd( BJTdum ntie )
vpnpColl = geomAnd( BJTdum ptie )
vpnpEmit = geomAnd( BJTdum ptox )
vpnp = geomEnclose( BJTdum vpnpEmit )
vpnpm1 = geomAnd( BJTdum Metal1 )
vpnpm2 = geomAnd( BJTdum Metal2 )
vpnpm3 = geomAnd( BJTdum Metal3 )
bjtCont = geomAnd( Cont geomOr( BJTdum NPNdummy PNPdummy ) )
Cont = geomAndNot( Cont bjtCont )

/* need to exclude metal inside BJTdumy for parasitic extraction purposes */

Metal1 = geomAndNot( Metal1 vpnpm1 )
m1vpnpConnector = geomAnd( geomSize( Metal1 .01) geomSize( vpnpm1 .01 ) )
m1vpnpCont = geomAnd( Metal1 m1vpnpConnector )
vpnpm1Cont = geomAnd( vpnpm1 m1vpnpConnector )

Metal2 = geomAndNot( Metal2 vpnpm2 )
m2vpnpConnector = geomAnd( geomSize( Metal2 .01) geomSize( vpnpm2 .01 ) )
m2vpnpCont = geomAnd( Metal2 m2vpnpConnector )
vpnpm2Cont = geomAnd( vpnpm2 m2vpnpConnector )

Metal3 = geomAndNot( Metal3 vpnpm3 )
m3vpnpConnector = geomAnd( geomSize( Metal3 .01) geomSize( vpnpm3 .01 ) )
m3vpnpCont = geomAnd( Metal3 m3vpnpConnector )
vpnpm3Cont = geomAnd( vpnpm3 m3vpnpConnector )


/* npn derivation */
npnBase = geomAnd( geomAnd( geomAnd( NPNdummy Nburied ) Pwell ) PPOD )
npnColl = geomAnd( geomAndNot( geomAnd( NPNdummy Nburied ) Pwell ) NPOD )
npnEmit = geomAnd( geomAnd( geomAnd( NPNdummy Nburied ) Pwell ) NPOD )
npn = geomEnclose( NPNdummy npnEmit )
npnm1 = geomAnd( NPNdummy Metal1 )
npnm2 = geomAnd( NPNdummy Metal2 )
npnm3 = geomAnd( NPNdummy Metal3 )

/* need to exclude metal inside NPNdummy for parasitic extraction purposes */

Metal1 = geomAndNot( Metal1 npnm1 )
m1npnConnector = geomAnd( geomSize( Metal1 .01) geomSize( npnm1 .01 ) )
m1npnCont = geomAnd( Metal1 m1npnConnector )
npnm1Cont = geomAnd( npnm1 m1npnConnector )

Metal2 = geomAndNot( Metal2 npnm2 )
m2npnConnector = geomAnd( geomSize( Metal2 .01) geomSize( npnm2 .01 ) )
m2npnCont = geomAnd( Metal2 m2npnConnector )
npnm2Cont = geomAnd( npnm2 m2npnConnector )

Metal3 = geomAndNot( Metal3 npnm3 )
m3npnConnector = geomAnd( geomSize( Metal3 .01) geomSize( npnm3 .01 ) )
m3npnCont = geomAnd( Metal3 m3npnConnector )
npnm3Cont = geomAnd( npnm3 m3npnConnector )


/* pnp derivation */
pnpBase = geomAnd( geomAnd( geomAnd( geomAnd( PNPdummy Nburied ) Pwell ) Nwell ) ntie )
pnpColl = geomAnd( geomAndNot( geomAnd( geomAnd( PNPdummy Nburied ) Pwell ) Nwell ) PPOD )
pnpEmit = geomAnd( geomAnd( geomAnd( PNPdummy Nburied) Pwell ) ptox )
pnp = geomEnclose( PNPdummy pnpEmit )
pnpm1 = geomAnd( PNPdummy Metal1 )
pnpm2 = geomAnd( PNPdummy Metal2 )
pnpm3 = geomAnd( PNPdummy Metal3 )

/* need to exclude metal inside PNPdummy for parasitic extraction purposes */

Metal1 = geomAndNot( Metal1 pnpm1 )
m1pnpConnector = geomAnd( geomSize( Metal1 .01) geomSize( pnpm1 .01 ) )
m1pnpCont = geomAnd( Metal1 m1pnpConnector )
pnpm1Cont = geomAnd( pnpm1 m1pnpConnector )

Metal2 = geomAndNot( Metal2 pnpm2 )
m2pnpConnector = geomAnd( geomSize( Metal2 .01) geomSize( pnpm2 .01 ) )
m2pnpCont = geomAnd( Metal2 m2pnpConnector )
pnpm2Cont = geomAnd( pnpm2 m2pnpConnector )

Metal3 = geomAndNot( Metal3 pnpm3 )
m3pnpConnector = geomAnd( geomSize( Metal3 .01) geomSize( pnpm3 .01 ) )
m3pnpCont = geomAnd( Metal3 m3pnpConnector )
pnpm3Cont = geomAnd( pnpm3 m3pnpConnector )


/* inductor derivation */
m3Ind = geomAnd( geomAnd( Metal3 IND2dummy ) INDdummy )
v2Ind = geomAnd( Via2 m3Ind )
Via2 = geomAndNot( Via2 v2Ind )
m2Ind = geomAnd( geomAnd( Metal2 IND2dummy ) INDdummy )
inductor = geomAnd( INDdummy m3Ind )

m2Pieces = geomAndNot( m2Ind m3Ind )
m2IndPlus = geomStraddle( m2Ind m2Pieces )
m2IndMinus = geomAndNot( m2Ind m2IndPlus )

inddmym2 = geomAnd( Metal2 INDdummy )
m2IndInt = geomAndNot( inddmym2 geomOr( m2IndPlus m2IndMinus ) )

m2IntIndPlusConnector = geomAnd( geomSize( m2IndInt .01 ) geomSize( m2IndPlus .01 ) )
m2IntIndPlusCont = geomAnd( m2IndInt m2IntIndPlusConnector )
m2PlusCont = geomAnd( m2IndPlus m2IntIndPlusConnector )

m2IntIndMinusConnector = geomAnd( geomSize( m2IndInt .01 ) geomSize( m2IndMinus .01 ) )
m2IntIndMinusCont = geomAnd( m2IndInt m2IntIndMinusConnector )
m2MinusCont = geomAnd( m2IndMinus m2IntIndMinusConnector )

/* need to exclude metal2 and metal3 inside IND2dummy for parasitic extraction purposes */

Metal2 = geomAndNot( Metal2 inddmym2 )
m2IntInddmyConnector = geomAnd( geomSize( Metal2 .01) geomSize( m2IndInt .01 ) )
m2IntInddmyCont = geomAnd( Metal2 m2IntInddmyConnector )
Inddmym2Cont = geomAnd( m2IndInt m2IntInddmyConnector )

inddmym3 = geomAnd( Metal3 INDdummy )
Metal3 = geomAndNot( Metal3 inddmym3 )
m3IntInddmyConnector = geomAnd( geomSize( Metal3 .01) geomSize( inddmym3 .01 ) )
m3IntInddmyCont = geomAnd( Metal3 m3IntInddmyConnector )
Inddmym3Cont = geomAnd( inddmym3 m3IntInddmyConnector )

;Need to derive various inductor shapes in order to properly extractor parameters.
;(this code assumes that the maximum inductor metal spacing is 20um)

m2outsideInd = geomAndNot( inddmym2 IND2dummy )
sized_m3Ind = geomSize( geomSize( m3Ind 9 ) -9 )
m3Ind_hole = geomHoles( sized_m3Ind )
dummy_area = geomAndNot( IND2dummy geomOr( sized_m3Ind m3Ind_hole ) )
m3Ind_separation_blocks = drc( m3Ind notch < 20 opposite shielded )
m3Ind_separation_area = geomAndNot( drc( m3Ind notch < 20 shielded ) geomOr( m3Ind_hole dummy_area ) )

/* need to separate out poly Interconnect for parasitic extraction purposes (don't
want to extract parasitic c on gates, poly caps etc) */

gate = geomOr( nmos pmos nmoscap )
polyInt = geomAndNot( Poly gate )
polyIntConnector = geomAnd( geomSize( polyInt .01) geomSize( gate .01 ) )
polyIntCont = geomAnd( polyInt polyIntConnector )
gateCont = geomAnd( gate polyIntConnector )


/* Establish connectivity */
geomConnect(

;via connects
via( Cont polyInt ndiff pdiff ntie ptie nmoscapm1 Metal1 pdiodePlus ndiodeMinus )
via( bjtCont vpnpEmit vpnpBase vpnpColl ptie vpnpm1 )
via( bjtCont npnEmit npnBase npnColl npnm1 )
via( bjtCont pnpEmit pnpBase pnpColl pnpm1 )
via( Via1 Metal1 nmoscapm1 vpnpm1 pnpm1 npnm1 Metal2 nmoscapm2 vpnpm2 pnpm2 npnm2 )
via( Via2 Metal2 vpnpm2 pnpm2 npnm2 Metal3 vpnpm3 pnpm3 npnm3 )
via( Via3 Metal3 Metal4 )
via( Via4 Metal4 Metal5 )
via( Via5 Metal5 Metal6 )

;poly connects
via( gateCont polyIntConnector gate )
via( polyIntCont polyIntConnector polyInt )
via( m1MoscapCont m1MoscapConnector Metal1 )
via( Moscapm1Cont m1MoscapConnector nmoscapm1 )
via( m2MoscapCont m2MoscapConnector Metal2 )
via( Moscapm2Cont m2MoscapConnector nmoscapm2 )

;vpnp connects
via( m1vpnpCont m1vpnpConnector Metal1 )
via( vpnpm1Cont m1vpnpConnector vpnpm1 )
via( m2vpnpCont m2vpnpConnector Metal2 )
via( vpnpm2Cont m2vpnpConnector vpnpm2 )
via( m3vpnpCont m3vpnpConnector Metal3 )
via( vpnpm3Cont m3vpnpConnector vpnpm3 )

;npn connects
via( m1npnCont m1npnConnector Metal1 )
via( npnm1Cont m1npnConnector npnm1 )
via( m2npnCont m2npnConnector Metal2 )
via( npnm2Cont m2npnConnector npnm2 )
via( m3npnCont m3npnConnector Metal3 )
via( npnm3Cont m3npnConnector npnm3 )

;pnp connects
via( m1pnpCont m1pnpConnector Metal1 )
via( pnpm1Cont m1pnpConnector pnpm1 )
via( m2pnpCont m2pnpConnector Metal2 )
via( pnpm2Cont m2pnpConnector pnpm2 )
via( m3pnpCont m3pnpConnector Metal3 )
via( pnpm3Cont m3pnpConnector pnpm3 )

;inductor connects
via( m2IntIndPlusCont m2IntIndPlusConnector m2IndInt )
via( m2PlusCont m2IntIndPlusConnector m2IndPlus )
via( m2IntIndMinusCont m2IntIndMinusConnector m2IndInt )
via( m2MinusCont m2IntIndMinusConnector m2IndMinus )
via( m2IntInddmyCont m2IntInddmyConnector Metal2 )
via( Inddmym2Cont m2IntInddmyConnector m2IndInt )
via( m3IntInddmyCont m3IntInddmyConnector Metal3 )
via( Inddmym3Cont m3IntInddmyConnector inddmym3 )
via( v2Ind m2Ind m3Ind )

;capacitor connects
via( m2IntCapCont m2IntCapConnector Metal2 )
via( capm2Cont m2IntCapConnector capm2 )
via( m3IntCapCont m3IntCapConnector Metal3 )
via( capm3Cont m3IntCapConnector capm3 )
via( capv23 CapMetal capm3 )

label( mt1_text Metal1 )
label( mt2_text Metal2 )
label( mt3_text Metal3 )
label( mt4_text Metal4 )
label( mt5_text Metal5 )
label( mt6_text Metal6 )

)

ivIf( (switch "Skip_Soft-Connect_Checks") then

geomStamp( Psub ptie )
geomStamp( Nwell ntie )

else

geomStamp( Psub ptie error)
geomStamp( Nwell ntie error)

) ;endif


/* Device Recognition & Parameter Extraction */

/* nmos */
extractDevice( "nmos" nmos gate("G") ndiff("S" "D") Psub("B") physical flagMalformed )

l_NMOS = measureParameter( length ( nmos inside Poly ) 0.5 )
w_NMOS = measureParameter( length ( nmos coincident Poly ) 0.5 )
normalizedl_NMOS = calculateParameter( l_NMOS * 1e-6 )
normalizedw_NMOS = calculateParameter( w_NMOS * 1e-6 )

nameParameter( normalizedl_NMOS "l" )
nameParameter( normalizedw_NMOS "w" )
nameParameter( normalizedw_NMOS "effW" )


/* pmos */
extractDevice( "pmos" pmos gate("G") pdiff("S" "D") Nwell("B") physical flagMalformed )

l_PMOS = measureParameter( length ( pmos inside Poly ) 0.5 )
w_PMOS = measureParameter( length ( pmos coincident Poly ) 0.5 )
normalizedl_PMOS = calculateParameter( l_PMOS * 1e-6 )
normalizedw_PMOS = calculateParameter( w_PMOS * 1e-6 )

nameParameter( normalizedl_PMOS "l" )
nameParameter( normalizedw_PMOS "w" )
nameParameter( normalizedw_PMOS "effW" )


/* polyres (rectangle) */
extractDevice( "polyres" polyres polyInt("PLUS" "MINUS") flagMalformed )

width = measureParameter( length (polyres butting Poly ) 0.5 )
normalizedWidth = calculateParameter( width * 1e-6 )
perimlength = measureParameter( length ( polyres coincident Resdum ) 0.5 )
length = calculateParameter( perimlength - width )
normalizedLength = calculateParameter( length * 1e-6 )

res = calculateParameter( (length * 7.5) / width )

nameParameter( normalizedWidth "w" )
nameParameter( normalizedWidth "wSim" )
nameParameter( normalizedLength "l" )
nameParameter( normalizedLength "lSim" )
nameParameter( res "r" )


/* nplusres rectangle */
extractDevice( "nplusres" nplusres ndiff("PLUS" "MINUS") Psub("B") flagMalformed )

width = measureParameter( length ( nplusres inside Oxide ) 0.5 )
normalizedWidth = calculateParameter( width * 1e-6 )
perimlength = measureParameter( length ( nplusres coincident Resdum ) 0.5 )
length = calculateParameter( perimlength - width )
normalizedLength = calculateParameter( length * 1e-6 )

res = calculateParameter( (length * 300) / width )

nameParameter( normalizedWidth "w" )
nameParameter( normalizedWidth "wSim" )
nameParameter( normalizedLength "l" )
nameParameter( normalizedLength "lSim" )
nameParameter( res "r" )


/* nmoscap */
extractDevice( "nmoscap" nmoscap gate("TOP") ndiff("BOT") Psub("B") flagMalformed )

w = measureParameter( length ( nmoscap coincident Poly) 0.5 )
normalizedWidth = calculateParameter( w * 1e-6 )
capPerim = measureParameter( perimeter ( nmoscap ) )
l = calculateParameter( ( capPerim - ( 2 * w ) ) / 2 )
normalizedLength = calculateParameter( l * 1e-6 )
capArea = measureParameter( area ( nmoscap ) )
normalizedArea = calculateParameter( capArea * 1e-12 )

c = calculateParameter( normalizedArea * .00846338 )

nameParameter( normalizedWidth "w" )
nameParameter( normalizedLength "l" )
nameParameter( c "c" )


/* mimcap */
extractDevice( "mimcap" mimcap CapMetal("PLUS") capm2("MINUS") flagMalformed )

capArea = measureParameter( area ( mimcap ) )
capPerim = measureParameter( perimeter ( mimcap ) )

capL = calculateParameter( sqrt( capArea ) )
normalizedL = calculateParameter( capL * 1e-6 )

cap = calculateParameter( (capArea * .1e-15) + (capPerim * .01e-15) )

nameParameter( cap "c" )
nameParameter( normalizedL "l" )
nameParameter( normalizedL "w" )


/* vpnp */
extractDevice( "vpnp" vpnp vpnpEmit("E") vpnpBase("B") vpnpColl("C") flagMalformed )

emitArea = measureParameter( area ( vpnp over vpnpEmit ) )
normalizedEmitArea = calculateParameter( emitArea * 1e-12 )

nameParameter( normalizedEmitArea "area" )

/* npn */
extractDevice( "npn" npn npnEmit("E") npnBase("B") npnColl("C") flagMalformed )

emitArea = measureParameter( area ( npn over npnEmit ) )
normalizedEmitArea = calculateParameter( emitArea * 1e-12 )

nameParameter( normalizedEmitArea "area" )


/* pnp */
extractDevice( "pnp" pnp pnpEmit("E") pnpBase("B") pnpColl("C") flagMalformed )

emitArea = measureParameter( area ( pnp over pnpEmit ) )
normalizedEmitArea = calculateParameter( emitArea * 1e-12 )

nameParameter( normalizedEmitArea "area" )


/* inductor */
extractDevice( "inductor" inductor m2IndMinus("MINUS") m2IndPlus("PLUS") physical flagMalformed )
; Constants:
k1 = 2.34
k2 = 2.75
u0 = (4e-7 * 3.14)

width = measureParameter( length (inductor butting m2outsideInd ) 0.5 )
normalizedWidth = calculateParameter( width * 1e-6 )

total_turns = measureParameter( bends_all ( inductor ) )
turns = calculateParameter( total_turns / 4 )

separation_block_perim = measureParameter( length ( inductor butting m3Ind_separation_blocks ) )
tot_separation_perim = measureParameter( length ( inductor butting m3Ind_separation_area ) )
sep = calculateParameter( (tot_separation_perim - separation_block_perim) / ((total_turns - 4) * 2) )
normalizedSep = calculateParameter( sep * 1e-6 )

total_perim = measureParameter( length ( inductor butting m3Ind_hole ) )
radius = calculateParameter( (total_perim - ((2*width) + sep )) / 8 )
normalizedRad = calculateParameter( radius * 1e-6 )

part1 = calculateParameter( (k1 * u0 * turns * turns * (0.5 * ( (2 * normalizedRad +
(turns + 0.5) * normalizedWidth + (turns - 0.5) * normalizedSep) + (2 * normalizedRad) ) ) ) )

part2 = calculateParameter( (1 + k2 * ( ( (2 * normalizedRad + (turns + 0.5) *
normalizedWidth + (turns - 0.5) * normalizedSep) - (2 * normalizedRad) ) /
( (2 * normalizedRad + (turns + 0.5) * normalizedWidth + (turns - 0.5) *
normalizedSep) + (2 * normalizedRad) ) ) ) )

inductance = calculateParameter( part1 / part2 )

; inductance = calculateParameter( (k1 * u0 * turns * turns * (0.5 * ( (2 * normalizedRad +
; (turns + 0.5) * normalizedWidth + (turns - 0.5) * normalizedSep) + (2 * normalizedRad) )
; ) ) / (1 + k2 * ( ( (2 * normalizedRad + (turns + 0.5) * normalizedWidth + (turns - 0.5)
; * normalizedSep) - (2 * normalizedRad) ) / ( (2 * normalizedRad + (turns + 0.5) *
; normalizedWidth + (turns - 0.5) * normalizedSep) + (2 * normalizedRad) ) ) ) )

nameParameter( turns "nr" )
nameParameter( normalizedWidth "width" )
nameParameter( normalizedSep "space" )
nameParameter( normalizedRad "rad" )
nameParameter( inductance "ind" )


/* pdiode */
extractDevice( "pdio" pdiode pdiodePlus("PLUS") ntie("MINUS") flagMalformed )

area = measureParameter( area ( pdiode over pdiodePlus ) )
normalizedArea = calculateParameter( area * 1e-12 )

perim = measureParameter( perimeter ( pdiode over pdiodePlus ) )
normalizedPerim = calculateParameter( perim * 1e-6 )

nameParameter( normalizedArea "area" )
nameParameter( normalizedPerim "pj" )


/* ndiode */
extractDevice( "ndio" ndiode ptie("PLUS") ndiodeMinus("MINUS") flagMalformed )

area = measureParameter( area ( ndiode over ndiodeMinus ) )
normalizedArea = calculateParameter( area * 1e-12 )

perim = measureParameter( perimeter ( ndiode over ndiodeMinus ) )
normalizedPerim = calculateParameter( perim * 1e-6 )

nameParameter( normalizedArea "area" )
nameParameter( normalizedPerim "pj" )


) ;endif extract

) ;end drcExtractRules

 

[sdedov]

assura extractdevice physical

Pay you attention that the drain area is 0...

The extracted drain are is (ad=) 2.6861 in that perticular case. But when measured manually, its about 50% smaller. The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

As for the writing extraction rules, that is outside my knowlage. Perhaps that is the way to go if I want to get any results within a reasonoble scope. Tnx for the info, i will look into it.

Sorry, i meant the drain perimeter. If you have any drain, its area couldn't be 0 -).

If you have an Assura extraction rules, just find your device in
extractDevice section, ex. your device is "nmos"

extractDevice( "nmos" nmos gate("G") ndiff("S" "D") Psub("B") physical flagMalformed )

l_NMOS = measureParameter( length ( nmos inside Poly ) 0.5 )
w_NMOS = measureParameter( length ( nmos coincident Poly ) 0.5 )

and analyze how l,w,as,etc parameters are defined in measureParameter

BTW, extraction rules can include a special "switches" or "key" inside which defines the behaviour of extractor. In Calibre, for ex., "DEFINE" key. Try to read the header of extraction rules file.

 

[erikl]

vdd vg

The extracted drain area is (ad=) 2.6861 in that particular case. But when measured manually, it's about 50% smaller.
The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

How can the perimeter of any area ≠ 0 be 0 ?

 

[Yarrow]

assura extractdevice physical

The extracted drain area is (ad=) 2.6861 in that particular case. But when measured manually, it's about 50% smaller.
The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

How can the perimeter of any area ≠ 0 be 0 ?

I am sorry, its my english that has gone bad. "ps" and "pd" dont stand for source/drain perimeter, the correct term is periphery.The green line distanse in the attached file is the periphery of the source/drain in the linear transistor. (0.23+6.0+0.23 = 6.46)

Apperently the periphery in Cadence is handeled like the outer edge of an object.

What can be observed there is that the distance where poly and active region meet, is not taken into account when calculating the periphery. Therefore, an area enclosed by poly has the perimeter = 0.


@stedov: The Cadence kit I am currently using at the moment utilizes diveEXT.rul. However, after some consideration, I do not think writing new rules will give more credible simulation results. New extraction rules will help with the extraction of correct parameters, but in the end the simulation results wont be credibe i think? The reason for me assuming this is because the extracted parameters are used in some kind of simulation model that generates the transistor response. And if that simulation model does not take into account the effects ring transistors bring, then the simulation results will probobly be incorrect. I dont know if I am underestimating Cadence here, or perhaps my assumptions are totally off?


@erikl: By the way, I figured out how to use an edited netlist. I did some simulations based on what I thought were the correct parameters, and got a decrease in both leakage current (~-2nA) and gain. Althoug as previously stated, I am not totaly sure that I have measured the parameters correctly.

However, the only parameter I am still unsure about is the po2act. From the extraction of a linear transistor (the one attached), the po2act=0.23. This distance is the same as the distance between poly to the end of the active region. (illustrated by one of the green horisontal lines in the attached file) I tried to double the source/drain cut area, and the po2act parameter doubled. This may imply that the po2act has nothing to do with the periphery of the poly gate directly.


Anyways, I think the right way to go is 3D CAD tools using finite-element-method (FEM). At the moment I am trying to aquire such a tool (Synopsys Sentaurus TCAD) to provide me with more accurate simulation results. Hopefully the CAD tool can be integrated with Cadence to enable for simulations on bigger cells then ones only containing a couple of transistors.

Furthermore it will be interesting to find out how much the simulation results differ from a FEM based CAD tool to a 2D layout tool like Cadence.

 

[erikl]

tutorial tcad sentaurus tool

The green line distance in the attached file is the periphery of the source/drain in the linear transistor. (0.23+6.0+0.23 = 6.46)

Apperently the periphery in Cadence is handeled like the outer edge of an object.

What can be observed there is that the distance where poly and active region meet, is not taken into account when calculating the periphery. Therefore, an area enclosed by poly has the perimeter = 0.

Surely you mean periphery again?
I understand the drain periphery pd = drain perimeter not adjacent to the poly gate.
The drain capacitance cd generally is computed as cd=(ad*areaCapValue/area-unit)+(pd*lengthCapValue/length-unit). As there's only a drain area junction (and no drain length junction not adjacent to the poly) inside a ring structure, I now understand why pd=0 for a ring structure MOSFET.

@erikl: By the way, I figured out how to use an edited netlist. I did some simulations based on what I thought were the correct parameters, and got a decrease in both leakage current (~-2nA) and gain. Althoug as previously stated, I am not totaly sure that I have measured the parameters correctly.

However, the only parameter I am still unsure about is the po2act. From the extraction of a linear transistor (the one attached), the po2act=0.23. This distance is the same as the distance between poly to the end of the active region. (illustrated by one of the green horisontal lines in the attached file) I tried to double the source/drain cut area, and the po2act parameter doubled. This may imply that the po2act has nothing to do with the periphery of the poly gate directly.

Anyways, I think the right way to go is 3D CAD tools using finite-element-method (FEM). At the moment I am trying to aquire such a tool (Synopsys Sentaurus TCAD) to provide me with more accurate simulation results. Hopefully the CAD tool can be integrated with Cadence to enable for simulations on bigger cells then ones only containing a couple of transistors.

Furthermore it will be interesting to find out how much the simulation results differ from a FEM based CAD tool to a 2D layout tool like Cadence.

Thank you for your feedBack!

 

[Yarrow]

transistor structure

Sorry, I ment periphery again, yes.

Thank you aswell! I felt it was nice to get some feedback on this type of problem. Its an important part of my design.