signed substraction in verilog

[Aimerbhat]

i synthesized my code (verilog) containing mainly additions and subtractions and am doing post synthesis simulation in modelsim

in modelsim wave i see,
instead to obtaining differences of two registers , i am now obtaining difference divide by 2

I am not able to figure out the problem.
i even tried re declaring wire resulted by subtraction as wire signed ...but still no change

what is the proper way to give signed operation instructions in verilog..

kindly help

regards
aimer

 

[rca]

do you use Logic Equivalent Checker to check RTL versus netlist?
because the synthesis can made some simplification, but the result is the same.