signaltap got a Strange problem (measuring intended signal)

[lichenjiee]

HI friends!
I copied the two FPGA projects ,One project signaltap I added two signal under test, another project I added three groups of signal under test. in both projects I were a group of the measured signal is a particular concern to me, but the end result output the signal of interest is completely different, which is how I judge this to be the signal of interest which is correct?

 

[ads-ee]

There is a severe lack of information and clarity to help with this question, which is why it has had so many views and no replies.

I copied the two FPGA projects

okay so what are the projects? are they identical (duplicates) or different or what? If they are a counter and a multiplexer then I wouldn't expect any signaltap signals to match.

in both projects I were a group of the measured signal is a particular concern to me, but the end result output the signal of interest is completely different,

What signals are you adding signaltap to? How is anyone supposed to know based on the above description. If you were to connect to an enable and a reset in one design and an enable and a reset in another design I wouldn't expect them to be the same unless the designs were identical with identical stimulus.

Describe your problem completely with code and anything that you are using/doing so someone here can help you with your problem.

Looking over your other posts seems to show that you likely have a weak grasp of the English language, is there someone you know that can assist in translating to/from English?

 

[matrixofdynamism]

please tell us more about the project

 

[lichenjiee]

I really appreciate for your post,and Due to the poor English description,i stop it.Fortunately,last two week,i fixed out this problem ,it's about timing constraints , at the beginning i have a bad Timing Closure in my system and make it unstable.