Signals with multiple drivers as wire

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asic_learner

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Signals with multiple drivers

Hi everyone,

I'm having a doubt.
Why signals with multiple drivers should be wires only, why can't they be reg or logic while declaring signals in verilog?

Thanks in advance
 
Last edited:

1-a register will be replace physically by a flop and the output couldn't by driven by an other cell, right?
2- a wire could connect two tris state outputs.
 

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