Signals with multiple drivers as wire

[asic_learner]

Signals with multiple drivers

Hi everyone,

I'm having a doubt.
Why signals with multiple drivers should be wires only, why can't they be reg or logic while declaring signals in verilog?

Thanks in advance

 

[rca]

1-a register will be replace physically by a flop and the output couldn't by driven by an other cell, right?
2- a wire could connect two tris state outputs.

 

[asic_learner]

Ohh ok
thanks

 

[dave_59]

I just published a short article on this: https://go.mentor.com/wire-vs-reg