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signal integrity with altium

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Siliconray

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Hi,

how often do you run signal integrity to test your PCB. What kind of terminations do you use.

I draw PCB which have components with 1ns rise time.I import IBIS models and setup layer structure. Most of tracks are shorter than 40mm(1.5inch) and their with is 6mils. I run Signal integrity(Altium) and I get unsatisfying results. All most every line need termination i think something is wrong here.

Could you advice me how to correct or get more relevant results?

r,S
 

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