Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Signal integrity issues with dynamic logic nets on normal nets

Status
Not open for further replies.

snr_vlsi

Member level 1
Joined
Jan 21, 2008
Messages
34
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,564
Hi,

Consider this scenario.

Consider an inverter with an input net and an output net connected it. There is a neighbouring net which is actually a floating net and there is no transition on this net.

What is the effect of this floating net in terms of signal integrity on the nets connected to inverter where there is a transition from low to high.

Does any one have any idea about signal integrity issues with dynamic logic nets on normal nets

i.e. dynamic logic nets are nets connected to logic gates that are precharged and does not transition.

thx

snr_vlsi
 

Signal Integrity

If this is static floating net then this cannot cause crosstalk delay/glitch on other nets. However, if there is an aggressor transitioning nearby, it may cause a glitch on this net.
 

Re: Signal Integrity

so you should make an analysis on this case whether cross talk and noise glitch will have impact in realtime!
 

Re: Signal Integrity

i think Navdeep is right
it will not have any effect but usually we tie it to ground as a precautionary measure
no net left ids left floating
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top