Signal has multiple drivers

[thetrice]

Error appears in translate phase that signal clkin2 has multiple drivers although it doesnt , main clock signal enters a DCM which generates 2 clock singles 1 acts as a clock for my vhdl module and other act as a clock for microblaze , the clkin2 is the clock of microblaze and its telling me it has multiple drivers .. here is the code for my top vhdl :

-------------------------------------------------------------------------------
-- micro_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity micro_top is
  port (
 -- clkin: in  std_logic;
    fpga_0_RS232_Uart_1_RX_pin : in std_logic;
    fpga_0_RS232_Uart_1_TX_pin : out std_logic;
    fpga_0_DIP_Switches_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
    fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
    fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
    fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
    fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
    fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
    fpga_0_Ethernet_MAC_MDINT_pin : in std_logic;
     LED: out std_logic_vector(3 downto 0);
    fpga_0_MCB_DDR3_mcbx_dram_addr_pin : out std_logic_vector(12 downto 0);
    fpga_0_MCB_DDR3_mcbx_dram_ba_pin : out std_logic_vector(2 downto 0);
    fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_we_n_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_cke_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_clk_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_dq_pin : inout std_logic_vector(15 downto 0);
    fpga_0_MCB_DDR3_mcbx_dram_dqs_pin : inout std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin : inout std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_udqs_pin : inout std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin : inout std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_udm_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_ldm_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_odt_pin : out std_logic;
    fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin : out std_logic;
    fpga_0_MCB_DDR3_rzq_pin : inout std_logic;
    fpga_0_MCB_DDR3_zio_pin : inout std_logic;
    fpga_0_clk_1_sys_clk_p_pin : in std_logic;
    fpga_0_clk_1_sys_clk_n_pin : in std_logic;
    fpga_0_rst_1_sys_rst_pin : in std_logic
--    xps_gpio_0_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_0_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_1_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_1_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_2_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_2_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_3_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_3_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
--    xps_gpio_4_GPIO_IO_O_pin : out std_logic_vector(0 to 3);
--    xps_gpio_5_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_5_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_6_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_6_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_7_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_7_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_8_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
--    xps_gpio_8_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
--    clock_generator_0_CLKOUT3_pin : out std_logic
  );
end micro_top;

architecture STRUCTURE of micro_top is
component mycode is
port(
clk:in std_logic;
Input_1:in std_logic_vector((32)-1 downto 0);
Input_2:in std_logic_vector((32)-1 downto 0);
Input_3:in std_logic_vector((32)-1 downto 0);
Input_4:in std_logic_vector((32)-1 downto 0);
Input_5:in std_logic_vector((32)-1 downto 0);
Input_6:in std_logic_vector((32)-1 downto 0);
Input_7:in std_logic_vector((32)-1 downto 0);
Input_8:in std_logic_vector((32)-1 downto 0);
ready:in std_logic_vector(3 downto 0);
state:out std_logic_vector(3 downto 0);
Output_1:out std_logic_vector((32)-1 downto 0);
Output_2:out std_logic_vector((32)-1 downto 0);
Output_3:out std_logic_vector((32)-1 downto 0);
Output_4:out std_logic_vector((32)-1 downto 0);
Output_5:out std_logic_vector((32)-1 downto 0);
Output_6:out std_logic_vector((32)-1 downto 0);
Output_7:out std_logic_vector((32)-1 downto 0);
Output_8:out std_logic_vector((32)-1 downto 0)
);
end component;
component clk_wiz_v3_6 is
port (-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic;
  CLK_OUT2          : out    std_logic
 );
end component;
  component micro is
    port (
      fpga_0_RS232_Uart_1_RX_pin : in std_logic;
      fpga_0_RS232_Uart_1_TX_pin : out std_logic;
      fpga_0_DIP_Switches_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
      fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
      fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
      fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
      fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
      fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
      fpga_0_Ethernet_MAC_MDINT_pin : in std_logic;
        fpga_0_MCB_DDR3_mcbx_dram_addr_pin : out std_logic_vector(12 downto 0);
      fpga_0_MCB_DDR3_mcbx_dram_ba_pin : out std_logic_vector(2 downto 0);
      fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_we_n_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_cke_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_clk_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_dq_pin : inout std_logic_vector(15 downto 0);
      fpga_0_MCB_DDR3_mcbx_dram_dqs_pin : inout std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin : inout std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_udqs_pin : inout std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin : inout std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_udm_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_ldm_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_odt_pin : out std_logic;
      fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin : out std_logic;
      fpga_0_MCB_DDR3_rzq_pin : inout std_logic;
      fpga_0_MCB_DDR3_zio_pin : inout std_logic;
      fpga_0_clk_1_sys_clk_p_pin : in std_logic;
      fpga_0_clk_1_sys_clk_n_pin : in std_logic;
      fpga_0_rst_1_sys_rst_pin : in std_logic;
      xps_gpio_0_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_0_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_1_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_1_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_2_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_2_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_3_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_3_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
      xps_gpio_4_GPIO_IO_O_pin : out std_logic_vector(0 to 3);
      xps_gpio_5_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_5_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_6_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_6_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_7_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_7_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_8_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
      xps_gpio_8_GPIO2_IO_O_pin : out std_logic_vector(0 to 31)
--      clock_generator_0_CLKOUT3_pin : out std_logic
    );
  end component;

 signal clkin :std_logic;
 -- signal feedback :std_logic;
  signal clkin2:std_logic;
    signal xps_gpio_0_GPIO_IO_I_pin :std_logic_vector(0 to 31);
    signal xps_gpio_0_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_1_GPIO_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_1_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_2_GPIO_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_2_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_3_GPIO_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_3_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
    signal xps_gpio_4_GPIO_IO_O_pin : std_logic_vector(0 to 3);
    signal xps_gpio_5_GPIO_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_5_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_6_GPIO_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_6_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_7_GPIO_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_7_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_8_GPIO_IO_O_pin : std_logic_vector(0 to 31);
    signal xps_gpio_8_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
     signal clock_generator_0_CLKOUT3_pin : std_logic;
  attribute BUFFER_TYPE : STRING;
 attribute BOX_TYPE : STRING;
  attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_tx_clk_pin : signal is "IBUF";
  attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_rx_clk_pin : signal is "IBUF";
 attribute BOX_TYPE of micro : component is "user_black_box";

begin
dcmer:clk_wiz_v3_6
  port map (
    CLK_IN1 =>fpga_0_clk_1_sys_clk_p_pin,
-- CLKFB_IN  =>  open,
  -- Clock out ports
  CLK_OUT1=>clkin,
  CLK_OUT2 =>clkin2
 -- CLKFB_OUT          =>  open
  );
unit1 : mycode  port map (
clk=>clkin,
Output_1=> xps_gpio_0_GPIO_IO_I_pin,
Output_2=> xps_gpio_0_GPIO2_IO_I_pin,
Output_3=> xps_gpio_1_GPIO_IO_I_pin,
Output_4=> xps_gpio_1_GPIO2_IO_I_pin,
Output_5=> xps_gpio_2_GPIO_IO_I_pin,
Output_6=> xps_gpio_2_GPIO2_IO_I_pin,
Output_7=> xps_gpio_3_GPIO_IO_I_pin,
Output_8=>  xps_gpio_3_GPIO2_IO_I_pin,
ready=>    xps_gpio_4_GPIO_IO_O_pin,
state=>LED,
Input_1=> xps_gpio_5_GPIO_IO_O_pin,
Input_2=> xps_gpio_5_GPIO2_IO_O_pin,
Input_3=> xps_gpio_6_GPIO_IO_O_pin,
Input_4=> xps_gpio_6_GPIO2_IO_O_pin,
Input_5=> xps_gpio_7_GPIO_IO_O_pin,
Input_6=> xps_gpio_7_GPIO2_IO_O_pin,
Input_7=> xps_gpio_8_GPIO_IO_O_pin,
Input_8=> xps_gpio_8_GPIO2_IO_O_pin
);
--LED<=xps_gpio_4_GPIO_IO_O_pin;

  micro_i : micro
    port map (
      fpga_0_RS232_Uart_1_RX_pin => fpga_0_RS232_Uart_1_RX_pin,
      fpga_0_RS232_Uart_1_TX_pin => fpga_0_RS232_Uart_1_TX_pin,
      fpga_0_DIP_Switches_4Bit_GPIO_IO_pin => fpga_0_DIP_Switches_4Bit_GPIO_IO_pin,
      fpga_0_Ethernet_MAC_PHY_tx_clk_pin => fpga_0_Ethernet_MAC_PHY_tx_clk_pin,
      fpga_0_Ethernet_MAC_PHY_rx_clk_pin => fpga_0_Ethernet_MAC_PHY_rx_clk_pin,
      fpga_0_Ethernet_MAC_PHY_crs_pin => fpga_0_Ethernet_MAC_PHY_crs_pin,
      fpga_0_Ethernet_MAC_PHY_dv_pin => fpga_0_Ethernet_MAC_PHY_dv_pin,
      fpga_0_Ethernet_MAC_PHY_rx_data_pin => fpga_0_Ethernet_MAC_PHY_rx_data_pin,
      fpga_0_Ethernet_MAC_PHY_col_pin => fpga_0_Ethernet_MAC_PHY_col_pin,
      fpga_0_Ethernet_MAC_PHY_rx_er_pin => fpga_0_Ethernet_MAC_PHY_rx_er_pin,
      fpga_0_Ethernet_MAC_PHY_rst_n_pin => fpga_0_Ethernet_MAC_PHY_rst_n_pin,
      fpga_0_Ethernet_MAC_PHY_tx_en_pin => fpga_0_Ethernet_MAC_PHY_tx_en_pin,
      fpga_0_Ethernet_MAC_PHY_tx_data_pin => fpga_0_Ethernet_MAC_PHY_tx_data_pin,
      fpga_0_Ethernet_MAC_PHY_MDC_pin => fpga_0_Ethernet_MAC_PHY_MDC_pin,
      fpga_0_Ethernet_MAC_PHY_MDIO_pin => fpga_0_Ethernet_MAC_PHY_MDIO_pin,
      fpga_0_Ethernet_MAC_MDINT_pin => fpga_0_Ethernet_MAC_MDINT_pin,
      fpga_0_MCB_DDR3_mcbx_dram_addr_pin => fpga_0_MCB_DDR3_mcbx_dram_addr_pin,
      fpga_0_MCB_DDR3_mcbx_dram_ba_pin => fpga_0_MCB_DDR3_mcbx_dram_ba_pin,
      fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin => fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin => fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_we_n_pin => fpga_0_MCB_DDR3_mcbx_dram_we_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_cke_pin => fpga_0_MCB_DDR3_mcbx_dram_cke_pin,
      fpga_0_MCB_DDR3_mcbx_dram_clk_pin => fpga_0_MCB_DDR3_mcbx_dram_clk_pin,
      fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin => fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_dq_pin => fpga_0_MCB_DDR3_mcbx_dram_dq_pin,
      fpga_0_MCB_DDR3_mcbx_dram_dqs_pin => fpga_0_MCB_DDR3_mcbx_dram_dqs_pin,
      fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin => fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_udqs_pin => fpga_0_MCB_DDR3_mcbx_dram_udqs_pin,
      fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin => fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin,
      fpga_0_MCB_DDR3_mcbx_dram_udm_pin => fpga_0_MCB_DDR3_mcbx_dram_udm_pin,
      fpga_0_MCB_DDR3_mcbx_dram_ldm_pin => fpga_0_MCB_DDR3_mcbx_dram_ldm_pin,
      fpga_0_MCB_DDR3_mcbx_dram_odt_pin => fpga_0_MCB_DDR3_mcbx_dram_odt_pin,
      fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin => fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin,
      fpga_0_MCB_DDR3_rzq_pin => fpga_0_MCB_DDR3_rzq_pin,
      fpga_0_MCB_DDR3_zio_pin => fpga_0_MCB_DDR3_zio_pin,
      fpga_0_clk_1_sys_clk_p_pin => clkin2,
      fpga_0_clk_1_sys_clk_n_pin => fpga_0_clk_1_sys_clk_n_pin,
      fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
      xps_gpio_0_GPIO_IO_I_pin => xps_gpio_0_GPIO_IO_I_pin,
      xps_gpio_0_GPIO2_IO_I_pin => xps_gpio_0_GPIO2_IO_I_pin,
      xps_gpio_1_GPIO_IO_I_pin => xps_gpio_1_GPIO_IO_I_pin,
      xps_gpio_1_GPIO2_IO_I_pin => xps_gpio_1_GPIO2_IO_I_pin,
      xps_gpio_2_GPIO_IO_I_pin => xps_gpio_2_GPIO_IO_I_pin,
      xps_gpio_2_GPIO2_IO_I_pin => xps_gpio_2_GPIO2_IO_I_pin,
      xps_gpio_3_GPIO_IO_I_pin => xps_gpio_3_GPIO_IO_I_pin,
      xps_gpio_3_GPIO2_IO_I_pin => xps_gpio_3_GPIO2_IO_I_pin,
      xps_gpio_4_GPIO_IO_O_pin => xps_gpio_4_GPIO_IO_O_pin,
      xps_gpio_5_GPIO_IO_O_pin => xps_gpio_5_GPIO_IO_O_pin,
      xps_gpio_5_GPIO2_IO_O_pin => xps_gpio_5_GPIO2_IO_O_pin,
      xps_gpio_6_GPIO_IO_O_pin => xps_gpio_6_GPIO_IO_O_pin,
      xps_gpio_6_GPIO2_IO_O_pin => xps_gpio_6_GPIO2_IO_O_pin,
      xps_gpio_7_GPIO_IO_O_pin => xps_gpio_7_GPIO_IO_O_pin,
      xps_gpio_7_GPIO2_IO_O_pin => xps_gpio_7_GPIO2_IO_O_pin,
      xps_gpio_8_GPIO_IO_O_pin => xps_gpio_8_GPIO_IO_O_pin,
      xps_gpio_8_GPIO2_IO_O_pin => xps_gpio_8_GPIO2_IO_O_pin
     -- clock_generator_0_CLKOUT3_pin => clock_generator_0_CLKOUT3_pin
    );

end architecture STRUCTURE;

and here is the code of DCM component :

-- file: clk_wiz_v3_6.vhd
-- 
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-- 
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- 
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
-- 
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- PART OF THIS FILE AT ALL TIMES.
-- 
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
-- CLK_OUT2___100.000______0.000_______N/A________0.000________N/A
--
------------------------------------------------------------------------------
-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity clk_wiz_v3_6 is
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic;
  CLK_OUT2          : out    std_logic
 );
end clk_wiz_v3_6;

architecture xilinx of clk_wiz_v3_6 is
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=5.0,clkin2_period=5.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
  -- Input clock buffering / unused connectors
  signal clkin1            : std_logic;
  -- Output clock buffering / unused connectors
  signal clkfx             : std_logic;
  signal clkfx180_unused   : std_logic;
  signal clkfxdv           : std_logic;
  signal clkfbout          : std_logic;
  -- Dynamic programming unused signals
  signal progdone_unused   : std_logic;
  signal locked_internal   : std_logic;
  signal status_internal   : std_logic_vector(2 downto 1);

begin


  -- Input buffering
  --------------------------------------
  clkin1_buf : IBUFG
  port map
   (O => clkin1,
    I => CLK_IN1);


  -- Clocking primitive
  --------------------------------------
  -- Instantiation of the DCM primitive
  --    * Unused inputs are tied off
  --    * Unused outputs are labeled unused
  dcm_clkgen_inst: DCM_CLKGEN
  generic map
   (CLKFXDV_DIVIDE        => 2,
    CLKFX_DIVIDE          => 2,
    CLKFX_MULTIPLY        => 2,
    SPREAD_SPECTRUM       => "NONE",
    STARTUP_WAIT          => FALSE,
    CLKIN_PERIOD          => 5.0,
    CLKFX_MD_MAX          => 0.000)
  port map
   -- Input clock
   (CLKIN                 => clkin1,
    -- Output clocks
    CLKFX                 => clkfx,
    CLKFX180              => clkfx180_unused,
    CLKFXDV               => clkfxdv,
   -- Ports for dynamic phase shift
    PROGCLK               => '0',
    PROGEN                => '0',
    PROGDATA              => '0',
    PROGDONE              => progdone_unused,
   -- Other control and status signals
    FREEZEDCM             => '0',
    LOCKED                => locked_internal,
    STATUS                => status_internal,
    RST                   => '0');


  -- Output buffering
  -------------------------------------


  CLK_OUT1 <= clkfx;

  CLK_OUT2 <= clkfxdv;

end xilinx;

 

[kripacharya]

CLK_OUT2 =>clkin2

fpga_0_clk_1_sys_clk_p_pin => clkin2