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VHDL code - Can't resolve multiple constant drivers for net 'a'

jojo12

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If anyone can help it would be greatly appreciated.
I can't figure out how to specify a in the code to not get the error.

I'm getting this error for all a's (a(3), a(2), a(1), a(0))
Error (10028): Can't resolve multiple constant drivers for net "a[3]" at counter.vhd(20)

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
 
entity counter is
port (x : in std_logic_vector (3 downto 0);
clk : in std_ulogic;
y : out std_logic_vector (3 downto 0));
end entity counter;
architecture code_behavior of counter is
signal a: std_logic_vector (3 downto 0);
begin
process (clk)
begin
if rising_edge (clk) then a<= x;
end if;
end process;
process (x)
begin
if rising_edge (clk) then
 
if x < "1001" then y<=(a+"0001");
a<= a + "0001";
elsif x > "1001" then y<=(a-"0001");
a <= a - "0001";
else y<= "1001";
end if;
end if;
end process;
end architecture;

 
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FvM

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It's also wrong to use x in the sensitivity list of a clocked process. It has no effect in hardware synthesis but causes simulation mismatch. What's your intention?
 

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