signal doesnt go through ports

[buenos]

Hi

I have a multi-sourcefile VHDL project.
One of my signals drives some logic in another module.
I was analyzing my project with Xilinx chipscope pro, and monitoring the signal.
First, after synthesis one of the ports as a signal should have disappeared since the two ports are directly conneted. Second, Port-A value should have been alwas equal to port-B value, which was not.

module-1      TopLevel        module-2
-----------|          A        |---------------
  1-------[A]-----------------[B]------->0 (should be 1)
           |                   |
           |                   |
-----------|                   |---------------

What can cause this?

 

[lucbra]

I assume you have defined port A as output and port B as input?
Have you instantiated module-2 as a component in module-1?

Have you used the RTL viewer and physically can see port A and port B?

 

[buenos]

I assume you have defined port A as output and port B as input?
-yes

Have you instantiated module-2 as a component in module-1?
-both module 1 and 2 are instantiated in the toplevel file

Have you used the RTL viewer and physically can see port A and port B?
-the RTL viewer shows that the signal in module-1 is not goint to its port. Basically there is module-3 instantiated into module-1, module-3 and 1 both have the port-A, but the connection between the ports of module-1/3 are broken. Both module 1/3 has it as output, module-2 has it as input.

 

[lucbra]

Could you post some code?

What do you do with that signal in module-2. It might be optimized and removed ...

An attribute 'keep' on that local signal in module-2 can help ...

 

[buenos]

hi

here are some sources attached. I didnt attach the complete project.
The signal is:
pcieif_wb_burstlength
starting in the file xilinx_pcie2wb.vhd, going into the memory controller, but never arriving there.