Shift and Add multiplier Doesn't give required output

[sarjumaharaj]

Here is my code for shift and add multiplier (datapath controller method) Can anyone please see the code and see where I'm going wrong. It just doesn't seem to work.

The datapath is like this Datapath. However I've combined A and Q as prodandmulti in the code. because my professor told me that making product and multiplier individually caused problem while shifting.

I can upload the project file if you would like to test it yourself.

Here is the code. (ignore the codes in comments)

MAIN MODULE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity mainmodule is
	port (load , close ,clk : in std_logic;
			ext_multiplier, ext_multiplicant : in std_logic_vector (4 downto 1) ;
			product : out std_logic_vector ( 8 downto 1) 
			); 
			
end mainmodule;

architecture Behavioral of mainmodule is

component controller_shiftaddmul is
	port ( clk , load  , q0 , close : in std_logic ;
			 iniq , inib , inia , shift , add : out std_logic  -- n counter out std_logic 
		  ); 
end component;

component datapath is
	port ( clk , add , inia , inib , iniq , shift : in std_logic ; 
			 ext_multiplier , ext_multiplicant : in std_logic_vector (4 downto 1); 
			 q0 : out std_logic ;
			 product : out std_logic_vector (8 downto 1) 
			); 
			 
end component;

signal Sq0 , Sinia,Sinib,siniq,Sshift, Sadd : std_logic ;
--sq0 signal that checks the LSB of Q to see whether we need to shift or add 
-- sinia b and q initilizes a b and q here a and q refer to the same component but
-- sinia initializes the last 8 digit and siniq the first 4 digit  seee the product mul component it will be clear
-- sshift sadd is shift and add signal 
begin

datapath1 : datapath port map (clk , sadd, sinia, sinib, siniq, sshift, ext_multiplier, ext_multiplicant , sq0 , product); 
controller1 : controller_shiftaddmul port map  (clk ,load, sq0, close , siniq, sinib ,sinia, sshift ,sadd); 

end Behavioral;

DATA PATH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity datapath is
	port ( clk , add , inia , inib , iniq , shift : in std_logic ; 
			 ext_multiplier , ext_multiplicant : in std_logic_vector (4 downto 1); 
			 q0 : out std_logic ;
			 product : out std_logic_vector (8 downto 1) 
			); 
			 
end datapath;

architecture Behavioral of datapath is


--
--component q_multiplier is
--	port ( a0 , clk, shift , ini : in std_logic ; 
--			 mul: in std_logic_vector ( 4 downto 1); 
--			 q0 : out std_logic ;
--			 temp_out : out std_logic_vector (4 downto 1)
--		   ); 
--end component ; 


--component a_product is
--	port (add , shift , ini ,clk : in std_logic ; 
--			in_prod: in std_logic_vector ( 4 downto 1); 
--			out_prod: out std_logic_vector ( 4 downto 1); 
--			a0: out std_logic ); 
--end component;

component prodandmulti is
	port (clk ,add, inia, iniq , shift : in std_logic ;
			multi : in std_logic_vector (4 downto 1 ); 
			a_in : in std_logic_vector (4 downto 1) ;
			A_OUT : out std_logic_vector ( 4 downto 1); 
			q0: out std_logic  ; 
			output : out std_logic_vector ( 8 downto 1) ); 
end component;


component ALU is
	port (multiplicant , product : in std_logic_vector ( 4 downto 1); 
			add , clk : in std_logic ; 
			Aluout : out std_logic_vector (4 downto 1 )
			); 
end component;


component b_multiplicant is
	port (add ,ini ,clk  : in std_logic ; 
			in_multiplicant : in std_logic_vector (4 downto 1) ; 
			out_multiplicant: out std_logic_vector (4 downto 1)
			);			
end component;

-- DONT SEE THE CODES IN COMMENTS:
-- prod_ALU output from the ALU after adding 
-- q0_control signal from the prodandmulti that goes to the controller basically the LSB of Q 
-- b_multi multiplicant that goes to ALU
-- prod_A is the product term that goes to the ALU for processing 

signal prod_ALU , prod_A:  std_logic_vector (4 downto 1);  -- ALU BATA MULTIPLIER MA JANEY SIGNAL RA ALU MA JANEY SIGNAL
--signal A_shift : std_logic ; 
signal q0_control: std_logic; 
signal B_multi : std_logic_vector (4 downto 1); 
--signal multiplier_output : std_logic_vector ( 4 downto 1); -- i dont know if this is required 
--signal a_product_out : std_logic_vector (4 downto 1); 
begin 

--A_shift <= a0; 

--multiplier:q_multiplier port map (A_shift , clk , shift, iniq, ext_multiplier,q0_control, multiplier_output); 
--product1 : a_product port map (add , shift , inia , clk , prod_ALU, prod_A, A_shift ); 
ALU1: ALU port map (  B_multi,prod_A, add, clk ,prod_ALU ); 
multiplicant: b_multiplicant port map (add , iniq, clk , ext_multiplicant , B_multi );
promul1 :  prodandmulti port map (clk , add ,inia , iniq, shift , ext_multiplier , prod_ALU, prod_A , q0_control , product); 

q0 <= q0_control; 
end Behavioral;

CONTROLLER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all; 


entity controller_shiftaddmul is
	port ( clk , load  , q0 , close : in std_logic ;
			 iniq , inib , inia , shift , add : out std_logic  -- n counter out std_logic 
		  ); 
end controller_shiftaddmul;

architecture Behavioral of controller_shiftaddmul is

type state_type is (start , loader , hold , addition , shiftrt , counter , closed ) ; 
signal sreg , snext : state_type ; 
--sreg is the present state 
--snext is the next state
--at each rising edge the next state is copied to present state 
signal sigN : std_logic_vector (3 downto 1); 
begin

process (clk ) 
begin 
 sigN <= "100"; 

if (clk'event and clk = '1' ) then 
	sreg <= snext ;
end if ; 

end process ;

process (sreg )
begin 
case sreg is 
	when start => 		inib <= '0' ; 
							iniq <= '0' ; 
							--loada <=  <= '0';
							inia <= '0'; 							
							sign <= "000"; 
							shift <= '0'; 
							add <= '0';
	
	
							if (load = '1') then 
								snext <= loader ; 
							else
								snext <= start ; 
							end if ;
							
	when loader => 	inib <= '1' ; 
							iniq <= '1' ; 
							--loada <=  <= '0';
							inia <= '1'; 							
							sign <= "100"; 
							shift <= '0'; 
							add <= '0'; 
							
							snext <= hold ; 
							
	when hold =>      inib <= '0' ; 
							iniq <= '0' ; 
							--loada <=  <= '0';
							inia <= '0'; 							
							--sign <= "10000";  -- esko value  k huncha khai kunni  
							shift <= '0'; -- i think sign is not required as it is a variable so change of state most likely
							add <= '0'; --wont affect the value 

							if (q0 ='0')  then  
								snext <= shiftrt ; 
							else 
								snext <= addition ; 
							end if ;
							
	when addition =>  inib <= '0' ; 
							iniq <= '0' ; 
							--loada <=  <= '1'; -- i think load a is not requred as there is already add signal which will do its work 
							inia <= '0'; 							
							--sign <= "10000"; 
							shift <= '0'; 
							add <= '1';
							
							snext <= shiftrt ; 
	
	when shiftrt =>   inib <= '0' ; 
							iniq <= '0' ; 
							--loada <=  <= '1'; -- i think load a is not requred as there is already add signal which will do its work 
							inia <= '0'; 							
							--sign <= "10000"; 
							shift <= '1'; 
							add <= '0';
							
							snext <= counter ; 
	
	when counter =>   sign <= sign - 1; 
							if ( sign /= "000") then 
								snext <= hold ; 
							else 
								if (close = '1') then 
									snext <= closed ; 
								else 
									snext <= start ; 
								end if ;
							end if ; 
							
	when others =>   snext <= start ; 
						
	end case ; 
end process ;
end Behavioral;

ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all; 
entity ALU is
	port (multiplicant , product : in std_logic_vector ( 4 downto 1); 
			add , clk : in std_logic ; 
			Aluout : out std_logic_vector (4 downto 1 )
			); 
end ALU;

architecture Behavioral of ALU is
signal temp : std_logic_vector ( 4 downto 1); 
begin

	process (clk)
	begin 
	if rising_edge(clk) then 
		if (add = '1' ) then 
			temp <= multiplicant + product ; 
		end if; 
	
	aluout <= temp ; 
	end if ;
	end process ;
end Behavioral;

Multiplicant

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity b_multiplicant is
	port (add ,ini ,clk  : in std_logic ; 
			in_multiplicant : in std_logic_vector (4 downto 1) ; 
			out_multiplicant: out std_logic_vector (4 downto 1)
			);			
end b_multiplicant;


architecture Behavioral of b_multiplicant is
signal temp_multiplicant :  std_logic_vector ( 4 downto 1) ; 
begin

process (clk , ini , add)
begin  
if (rising_edge(clk)) then 

	if (ini = '1' ) then 
		temp_multiplicant <= in_multiplicant; 
	end if ; 
	
	if (add = '1' ) then 
		out_multiplicant <= temp_multiplicant ; 
	end if ;
end if ;
end process ;

end Behavioral;

-- REPORT --
-- Once the first condition is run the second condition will give output 
-- But once the second condition is run it will give output regardless 
--of whether the second condition is false in the next clock cycle

Product and Multiplicant

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prodandmulti is
	port (clk ,add, inia, iniq , shift : in std_logic ;
			multi : in std_logic_vector (4 downto 1 ); 
			a_in : in std_logic_vector (4 downto 1) ;
			A_OUT : out std_logic_vector ( 4 downto 1); 
			q0: out std_logic  ; 
			output : out std_logic_vector ( 8 downto 1) ); 
end prodandmulti;

architecture Behavioral of prodandmulti is
signal promul : std_logic_vector ( 8 downto 1) ;

signal signal_q0: std_logic ; 
begin
process (clk ) 
begin 
if (clk'event and clk = '1' ) then 
	if (inia = '1' ) then 
		promul (8 downto 5) <= "0000" ; 
	end if ; 
	
	if (iniq = '1') then 
		promul (4 downto 1) <= multi  ; 
	end if ;
	
	signal_q0 <= promul(1); 
	
	if (shift  = '1' ) then 
		
		signal_q0 <= promul(1); 
		for i in 7 downto 1  loop
			promul(8-i) <= promul(9-i) ; 
		end loop ;
	
		promul(8) <= '0' ; 
		
	end if ;
	
--end if ; -- here end if is at the last 
	if ( add = '1' ) then 
		a_out <= promul(8 downto 5) ;
		promul ( 8 downto 5)<= a_in ; 
	end if ;
	q0 <= signal_q0; 
	output <= promul ; 
end if ; 
	
end process ;
end Behavioral;

 

[rca]

First tried to respect the case declare Sinia, used sinia.
It is good to reset flop elements like "promul" to start from a know state.
Be consistant sometime "clk'event.." sometime "rising_edge(clk)".
Usually, we count the vector starts from 0, to have weight corresponding, bit 0 as the weight of 2^0<=> 1 not 2^1=2!!

signal_q0 <= promul(1); --is it correct?
for i in 7 downto 1  loop
   promul(8-i) <= promul(9-i) ; 
end loop ;
promul(8) <= '0' ;

equivalent to: "promul <= '0' & promul(7 DOWNTO 2); --nothing to write in bit weight 1? strange

process (clk ) 
begin 
  sigN <= "100"; 
  if (clk'event and clk = '1' ) then 
  sreg <= snext ;
end if ; 
end process ;

why do you expect from this code?
register "sreg" and also registers for "sigN"?
sigN is sign?, two process which write the same signal, not possible??

I dont look at the waveform, the code isn't enough clean.