SFDR problem for track and hold circuit

[wael_wael]

hi friends
i have problem that i cant know how to measure the SFDR in my design, any way in the figure below u can see the fft of the output of track and hold, fs=50MS/s
fin=10MS/s
could some one help me how much the SFDR here, and how
regards

 

[santi001]

Based on the window that you have used for fft. you will know which all bins belong to signal. If that is not right then signal power will be distributed all over the place.

Then you can compare the signal power with next dominant harmonic within FS/2

 

[wael_wael]

could some one explain more in details? now i have 10 MS/s input how much the SFDR here?
thanx in advanced

 

[safwatonline]

20dB

 

[wael_wael]

thanx guys, i got it. but i still have one more question . is there any relationship between the unity gain frequency of the OTA and the SFDR,
regards

 

[safwatonline]

i guess that increasing the SR and/or GBW will enhance the SFDR.

 

[wael_wael]

is there any equations to approve that, on the other side Fs=50Ms/s, how much should be the Fu of the OTA?

 

[santi001]

In a -ve feedback circuit output should be some multiple of input.
Everything else is error. Which will be reduced by (1+A(f)β)

In freq domain this error will be reduced based on the gain of the OTA
at that frequency. Higher gain at higher frequency => more UGB.

On the other hand if over all transfer function will looks like LPF,
The total output inherent device noise will increase if the UGB increases.

 

[wael_wael]

thank u so much, ur advices are helping me well, any way my OTA has Fu=145MHz, i think i must increse it to get higher SFDR
regards

 

[safwatonline]

if i were u, i would try to check the specs using some behavior model first before implementation, like if u are doing a pipelined ADC then try to implement it using behavior model then add the non-idealities one after another (gain , SR , GBW, noise ....)to be sure that when u meet block specs it will work on the main system.
note that the non-linearity of a block (T&H for instance) will affect the whole non-linearity but it is not just the limiting factor other blocks will increase this non-linearity

 

[wael_wael]

thank u all, in fact i am looking to increase the SFDR factor but at same time i dont want toch the OTA because i have designed with PMOS as input, so i dont aspect much from pmos transistors for increasing the unity gain frequency and phase margin, i am going to design bootstrapped switch which can be a good soluation, same the figure below, so what u think about my idea , also how to simulate the switch (this is main matter now) any one intrested the paper is uploded for u
regards

 

[wael_wael]

could some one help, how to simulate the bootstrapped switch
regards

 

[safwatonline]

if u want to simulate just the switch then u should sample a sine wave on a cap using that switch and see the spectrum of the output (SNR, SFDR)

 

[wael_wael]

thanx sfwat i have done that, just i want make sure it was correct,
best regards