Several questions about STA

[energeticdin]

Hi all,

1. How operating voltage can be used to satisfy timing?

2. What is the difference between local-skew, global-skew and useful-skew?

3. What is meant by virtual clock definition and why do i need it?

4. Is it possible to reduce clock skew to zero

5. what are problems associated with skew and how to minimize it?

6. How to solve setup and Hold violations in the design?
For hold only way to incsert buffers
and For setup only way to upsize the cell and tweak the skew?

Din

 

[badola]

virtual clock sta

may be these will help you.....

 

[seanwu]

reg2reg hold violations

You can not reduce skew to zero since there is on-chip variation.

 

[dechen]

what is virtual clock in sta

operating voltage is a factor cell library, which has slow and fast corner

 

[dsairajkiran]

how to solve reg2reg hold

you cannot reduce the clock skew to zero because on chip variations.

virtual clock is used to constrain the input to output (timing path) in your design.

 

[ljxpjpjljx]

virtual clocks sta

sta is a difficult topic to discuss, many methods can fix hold and setup time violiation, the porblem is when to fix them!

 

[iwpia50s]

sta corner voltage

1. How operating voltage can be used to satisfy timing?

Higher operating voltage can cause faster slew, which sometimes can fix timing.

2. What is the difference between local-skew, global-skew and useful-skew?
Local-skew - skew between a reg2reg path
Global-skew - skew between all registers in a clock domain
useful-skew - to advance the clock in a reg2reg path in order to meet setup time.

3. What is meant by virtual clock definition and why do i need it?
Virtual clocks are defined on I/O because they real clock associated with them, however, they are considered startpoints and endpoints in STA, so they must have a clock. The latency is estimated to be the network latency of a clock tree, pre-cts.

4. Is it possible to reduce clock skew to zero
Not in a practical sense.

5. what are problems associated with skew and how to minimize it?
Skew is the difference in insertion delay to registers. If the skew is too large, then you fail timing.

6. How to solve setup and Hold violations in the design?
For hold only way to insert buffers (Correct)
For setup only way to upsize the cell and tweak the skew?
Or reduce the levels of logic from reg2reg, use fasted cells, swap pins, slow down the clock, etc...