several questions about pll's stability and verification?

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ithink

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hi, i have been designed a 48M pll,but i have no idea to verify its stability and correct. At the beginning of design, in order to attain 48M output frequency, we made some suppose,such as phase margin Φ=50°,loop bandwidth ω=20k,and so on; we design 2nd loop filter according these suppose and others, at last we use hspice to obtain perfect output. However above output is accepted in given the condition, how can i verify pll's phase margin and loop bandwidth in reverse?

thanks !
best wish to you,everyone!

ithink
2006.1.9
 

what is your comparison frequency fo PFD?2nd loop filter is enough.
Set the BW is 1/15 ~ 1/10 of Comp. freq. and phase margin is about 45 ~55 degree.

the Deans book is good reference 4 u.
 

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