ithink
Junior Member level 2

hi, i have been designed a 48M pll,but i have no idea to verify its stability and correct. At the beginning of design, in order to attain 48M output frequency, we made some suppose,such as phase margin Φ=50°,loop bandwidth ω=20k,and so on; we design 2nd loop filter according these suppose and others, at last we use hspice to obtain perfect output. However above output is accepted in given the condition, how can i verify pll's phase margin and loop bandwidth in reverse?
thanks !
best wish to you,everyone!
ithink
2006.1.9
thanks !
best wish to you,everyone!
ithink
2006.1.9