fakeha_s
Junior Member level 3
vhdl code for 7 segment display
I want to view my output on seve segment display,do I make a separate verilog file for the code designed for seve segment and use my output here or in the same verilog file (containing my code)i do instantiation
I want to view my output on seve segment display,do I make a separate verilog file for the code designed for seve segment and use my output here or in the same verilog file (containing my code)i do instantiation