SEU Effect in SRAM memory cell by using SILVACO

[Manzar Mahmud]

Hello,

I want to simulate SEU(Single Event Upset) effect in SRAM memory cell by SILVACO. In example which is given in silvaco is demonstrating SEU in a MOSFET with an external resistor and capacitor emulating a RAM cell. How can I simulate a SRAM memory cell which is consists of two back to back CMOS inverter with transistor.

It will be very helpful for me if you can give the SILVACO code for simulate the SRAM memory cell. Eagerly waiting for your reply. Thanks in advance.

 

[dick_freebird]

Code? What code?

Draw your circuit or enter your netlist, and apply a properly
scaled current pulse to whichever transistor you like (or all).
You can do this all from within Gateway (schematic driven)
or from a netlist sourced into SmartSpice.

The SmartSpice RadHard version is not commonly distributed
and you may not have the SEE features unless you got it from
Silvaco explicitly. But you can perform the task, "old school",
in any SPICE out there.

Maybe your RC RAM cell is supposed to emulate a DRAM.