How to fix the setup violation even after the path is fully optimized ? And commands…
You want to fix setup violation in "physical designing" ?
Does it mean you are in Layout phase ?
1. Check the STA status in early stages
If you are in layout phase, let check whether this path has violation in the placement phase, or synthesis phase.
If yes, please give the feedback to front end team also.
They have responsibility to take care the logic modification.
If no, this is layout issue. Please check the clock tree synthesis result regarding to clock latencies of this path.
2. you can make a useful skew to fix it. Just add buffer to change the clock latency to make the path MET.
But please take care its side-effect.
3. Please check if your design constraint have size-only/dont-touch attribute applied to the cell on the data path.
If there are, tool can not make it best effort in term of timing optimization.