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Setup time simulation problem

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gjei

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Hello guys , I have a big problem, I'll explain the situation. I have a master-slave d flip-flop with transmission gates , and would I calculate the setup time . Doing simulations have come to a conclusion , that I have found a certain value. This value was found with a parametric simulation in LTSpice by varying the arrival time of the input data and making it closer and closer to the active edge of the clock. The problem is that now I would like to plot the progress of the clock-to-q to vary the setup time so check what is the limit beyond which the clock-to-q diverges to infinity . Any ideas?
Thanks so much .
 

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