Dec 22, 2012 #1 N naavid Newbie level 6 Joined Dec 22, 2012 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,348 what is the minimmum setup time of a pulse triggered flip flop such as a master/slave JK or SR flip flop??
what is the minimmum setup time of a pulse triggered flip flop such as a master/slave JK or SR flip flop??
Dec 22, 2012 #2 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 That really depends on the manufacturing technology of your FPGA/ASIC. Generally, the tinier the size the lower the time (this is because of the lower parasitic capacitance of the transistors)... What device are you using ?
That really depends on the manufacturing technology of your FPGA/ASIC. Generally, the tinier the size the lower the time (this is because of the lower parasitic capacitance of the transistors)... What device are you using ?