Setup Time of pulse triggered flip flop Maser/slave or SR flip flop

[naavid]

what is the minimmum setup time of a pulse triggered flip flop such as a master/slave JK or SR flip flop??

 

[shaiko]

That really depends on the manufacturing technology of your FPGA/ASIC.
Generally, the tinier the size the lower the time (this is because of the lower parasitic capacitance of the transistors)...
What device are you using ?