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it is quite crucial for u to use set up & hold time analysis,because if they are not met,then ur sequential ckts might not function.it might result in loss of data or atleast a delay in the data.for eg,if the set up is not met,then previous data is latched.as for as i know,we don't generally have hold violations because,the clk2q delay takes care of the hold time..
i really don't know how these are taken into account in h-spice...
jus think over the concept how a D ff will work without violation..
Any controlled storage device latch or ff will need to have data stable before and after the clock edge for proper transmission to Q output.. u violate that simple the device fails.. It hits the functionality directly and hence cant be taken lightly..
Set up violations after amnufacture can be accepted as u decrease the max freq of operation and the job s done but hold violation occurs.. jus throw the chip out of the window.
Y hold violation not given importance then because with present tech ClK TO q DELAY TAKE CARES OF hold time violations..