Jun 3, 2021 #1 D dirac16 Member level 5 Joined Jan 20, 2021 Messages 87 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 677 I am reading a paper which has proposed an ADPLL with a custom 8b TDC. Throughout the TDC design it claims the following: To be robust in the settling transient, the 8bit TDC has a dynamic range equivalent to 2×TCKV unlike PLLs using narrow-range TDCs. Click to expand... So how can a wider dynamic range make difference in the robustness of the settling time?
I am reading a paper which has proposed an ADPLL with a custom 8b TDC. Throughout the TDC design it claims the following: To be robust in the settling transient, the 8bit TDC has a dynamic range equivalent to 2×TCKV unlike PLLs using narrow-range TDCs. Click to expand... So how can a wider dynamic range make difference in the robustness of the settling time?