Setting parts of logical path as "ideal" in Design Compiler

[popsika]

Hi!

I'm quite a newbie in using design compiler. I have parts in my design, which are not present in the actual later circuit, but which I need for the simulation. Because of that, these paths do not need to be considered in the STA. Therefore I marked them as false paths.
But now I have the problem, that some paths are starting in my "real" circuit and ending in my "fake" circuit. So I can not declare the whole path as a false path. Is there a possibility to mark all paths inside a component (I'm using VHDL) as "ideal" in terms of gate and wire delays? I just found the ideal attribute which seems to be used for clock paths.

Thanks in advance!

 

[dpaul]

I cannot answer you question directly, but as per info in the 1st paragraph I would like t say something.

"I have parts in my design, which are not present in the actual later circuit, but which I need for the simulation."

As one of the design rules, I have learnt up to now to keep everything which is not intended to be synthesized in the test-bench. It simplifies the steps during design, simulation and synthesis.
So you might try this design approach so as not face the problem described in the 2nd paragraph.

 

[popsika]

That's actually a good idea. I will try to outsource all these components from the actual circuit. Thank for the hint .

 

[dpaul]

That's actually a good idea. I will try to outsource all these components from the actual circuit. Thank for the hint .

It is actually a standard design practice. I am sure this procedure will help you now and for future designs.