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If a signal A_OUT is coming out of your block A, and is expected to go into another block B, and is expected to consume say tBns from the time it leaves block A and is consumed inside block B, by say some register, then your output delay value on the port A_OUT in the block A should be tBns.
Here I am assuming that block A and B are running off same clock.
Hope it helps,
Say logic inside the block B before being captured say require tb ns. Then your output delay for block A should be T-tb ns ,where T is clcok period. They synthesis tool try to optimize logic in block A to meeting your output timing delay requirement(T-Tb). Otherwisw the block B capture FF could not catch the data sent by blcok A. I hope you got it
all the timings are calculated reg-reg. in a partitioned design, you may not have all the signals leaving from q-pin. same is the case with the flop in the next partition. to account for total delay between these to flops you need set_input_delay and set_output_delay